6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-07 12:28:24 +00:00
Code Issues Projects Releases Wiki Activity

Combine the code to build VLDM and VSTM instructions, since they are

Browse Source 
mostly the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98402 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2010-03-13 00:43:32 +00:00
parent cbd056074c
commit 3943ac38c9
1 changed files with 14 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@@ -697,15 +697,19 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
else else
Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
if (isLd) {
if (isAM5) if (isAM5) {
// VLDMS, VLDMD // VLDM[SD}, VSTM[SD]
MachineOperand &MO = MI->getOperand(0);
BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
.addReg(Base, getKillRegState(BaseKill)) .addReg(Base, getKillRegState(isLd ? BaseKill : false))
.addImm(Offset).addImm(Pred).addReg(PredReg) .addImm(Offset)
.addImm(Pred).addReg(PredReg)
.addReg(Base, getDefRegState(true)) // WB base register .addReg(Base, getDefRegState(true)) // WB base register
.addReg(MI->getOperand(0).getReg(), RegState::Define); .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
else if (isAM2) getKillRegState(MO.isKill())));
} else if (isLd) {
if (isAM2)
// LDR_PRE, LDR_POST, // LDR_PRE, LDR_POST,
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
.addReg(Base, RegState::Define) .addReg(Base, RegState::Define)
@@ -717,13 +721,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
} else { } else {
MachineOperand &MO = MI->getOperand(0); MachineOperand &MO = MI->getOperand(0);
if (isAM5) if (isAM2)
// VSTMS, VSTMD
BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
.addImm(Pred).addReg(PredReg)
.addReg(Base, getDefRegState(true)) // WB base register
.addReg(MO.getReg(), getKillRegState(MO.isKill()));
else if (isAM2)
// STR_PRE, STR_POST // STR_PRE, STR_POST
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
.addReg(MO.getReg(), getKillRegState(MO.isKill())) .addReg(MO.getReg(), getKillRegState(MO.isKill()))