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Remove redundancy in setcc patterns using multiclass.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141715 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-11 21:40:01 +00:00
parent c055a8782e
commit 395d76c5a3
2 changed files with 43 additions and 44 deletions
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29
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -241,27 +241,8 @@ defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
ZERO_64>;
// setcc patterns
def : Pat<(seteq CPU64Regs:$lhs, CPU64Regs:$rhs),
(SLTiu64 (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
def : Pat<(setne CPU64Regs:$lhs, CPU64Regs:$rhs),
(SLTu64 ZERO_64, (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs))>;
def : Pat<(setle CPU64Regs:$lhs, CPU64Regs:$rhs),
(XORi (SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
def : Pat<(setule CPU64Regs:$lhs, CPU64Regs:$rhs),
(XORi (SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
def : Pat<(setgt CPU64Regs:$lhs, CPU64Regs:$rhs),
(SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
def : Pat<(setugt CPU64Regs:$lhs, CPU64Regs:$rhs),
(SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
def : Pat<(setge CPU64Regs:$lhs, CPU64Regs:$rhs),
(XORi (SLT64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
def : Pat<(setuge CPU64Regs:$lhs, CPU64Regs:$rhs),
(XORi (SLTu64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
def : Pat<(setge CPU64Regs:$lhs, immSExt16:$rhs),
(XORi (SLTi64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;
def : Pat<(setuge CPU64Regs:$lhs, immSExt16:$rhs),
(XORi (SLTiu64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;
defm : SeteqPats<CPU64Regs, SLTiu64, DXOR, SLTu64, ZERO_64>;
defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;

58
lib/Target/Mips/MipsInstrInfo.td
View File

@ -953,30 +953,48 @@ defm : MovzPats<CPURegs, MOVZ_I>;
defm : MovnPats<CPURegs, MOVN_I>;
// setcc patterns
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
(SLTiu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
(SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
Instruction SLTuOp, Register ZEROReg> {
def : Pat<(seteq RC:$lhs, RC:$rhs),
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
def : Pat<(setne RC:$lhs, RC:$rhs),
(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
}
def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
(XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
def : Pat<(setle RC:$lhs, RC:$rhs),
(XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
def : Pat<(setule RC:$lhs, RC:$rhs),
(XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
}
def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
(SLT CPURegs:$rhs, CPURegs:$lhs)>;
def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
(SLTu CPURegs:$rhs, CPURegs:$lhs)>;
multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
def : Pat<(setgt RC:$lhs, RC:$rhs),
(SLTOp RC:$rhs, RC:$lhs)>;
def : Pat<(setugt RC:$lhs, RC:$rhs),
(SLTuOp RC:$rhs, RC:$lhs)>;
}
def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
(XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
def : Pat<(setge RC:$lhs, RC:$rhs),
(XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
def : Pat<(setuge RC:$lhs, RC:$rhs),
(XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
}
def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
Instruction SLTiuOp> {
def : Pat<(setge RC:$lhs, immSExt16:$rhs),
(XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
}
defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
defm : SetlePats<CPURegs, SLT, SLTu>;
defm : SetgtPats<CPURegs, SLT, SLTu>;
defm : SetgePats<CPURegs, SLT, SLTu>;
defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
// select MipsDynAlloc
def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;