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[SystemZ] Fix incorrect use of RISBG for a zero-extended right shift

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We would wrongly transform the testcase into the equivalent of an AND with 1.
The problem was that, when testing whether the shifted-in bits of the right
shift were significant, we used the width of the final zero-extended result
rather than the width of the shifted value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-11-26 10:53:16 +00:00
parent 7c6be4d558
commit 396e080b34
2 changed files with 22 additions and 19 deletions
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27
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -688,23 +688,12 @@ bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG,
return false;
}
// RxSBG.Input is a shift of Count bits in the direction given by IsLeft.
// Return true if the result depends on the signs or zeros that are
// shifted in.
static bool shiftedInBitsMatter(RxSBGOperands &RxSBG, uint64_t Count,
bool IsLeft) {
// Work out which bits of the shift result are zeros or sign copies.
uint64_t ShiftedIn = allOnes(Count);
if (!IsLeft)
ShiftedIn <<= RxSBG.BitSize - Count;
// Rotate that mask in the same way as RxSBG.Input is rotated.
// Return true if any bits of (RxSBG.Input & Mask) are significant.
static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) {
// Rotate the mask in the same way as RxSBG.Input is rotated.
if (RxSBG.Rotate != 0)
ShiftedIn = ((ShiftedIn << RxSBG.Rotate) |
(ShiftedIn >> (64 - RxSBG.Rotate)));
// Fail if any of the zero or sign bits are used.
return (ShiftedIn & RxSBG.Mask) != 0;
Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)));
return (Mask & RxSBG.Mask) != 0;
}
bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
@ -781,7 +770,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
// Check that the extension bits are don't-care (i.e. are masked out
// by the final mask).
unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
if (shiftedInBitsMatter(RxSBG, RxSBG.BitSize - InnerBitSize, false))
if (maskMatters(RxSBG, allOnes(RxSBG.BitSize) - allOnes(InnerBitSize)))
return false;
RxSBG.Input = N.getOperand(0);
@ -802,7 +791,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
if (RxSBG.Opcode == SystemZ::RNSBG) {
// Treat (shl X, count) as (rotl X, size-count) as long as the bottom
// count bits from RxSBG.Input are ignored.
if (shiftedInBitsMatter(RxSBG, Count, true))
if (maskMatters(RxSBG, allOnes(Count)))
return false;
} else {
// Treat (shl X, count) as (and (rotl X, count), ~0<<count).
@ -830,7 +819,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
// Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
// count bits from RxSBG.Input are ignored.
if (shiftedInBitsMatter(RxSBG, Count, false))
if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count)))
return false;
} else {
// Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),

14
test/CodeGen/SystemZ/risbg-01.ll
View File

@ -456,3 +456,17 @@ define i64 @f40(i64 %foo, i64 *%dest) {
%and = and i64 %shl, 2147483647
ret i64 %and
}
; In this case the sign extension is converted to a pair of 32-bit shifts,
; which is then extended to 64 bits. We previously used the wrong bit size
; when testing whether the shifted-in bits of the shift right were significant.
define i64 @f41(i1 %x) {
; CHECK-LABEL: f41:
; CHECK: sll %r2, 31
; CHECK: sra %r2, 31
; CHECK: llgcr %r2, %r2
; CHECK: br %r14
%ext = sext i1 %x to i8
%ext2 = zext i8 %ext to i64
ret i64 %ext2
}