6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Add a new bit to SUnit to record whether a node has implicit physreg

Browse Source 
defs, regardless of whether they are actually used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67528 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-03-23 16:10:52 +00:00
parent f871ccb853
commit 3974667c1a
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -245,6 +245,7 @@ namespace llvm {
bool isTwoAddress : 1; // Is a two-address instruction.
bool isCommutable : 1; // Is a commutable instruction.
bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
bool isPending : 1; // True once pending.
bool isAvailable : 1; // True once available.
bool isScheduled : 1; // True once scheduled.
@ -265,6 +266,7 @@ namespace llvm {
: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isCloned(false),
isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@ -276,6 +278,7 @@ namespace llvm {
: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isCloned(false),
isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@ -286,6 +289,7 @@ namespace llvm {
: Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0),
Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isCloned(false),
isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),

9
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -41,6 +41,7 @@ SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
SU->isTwoAddress = Old->isTwoAddress;
SU->isCommutable = Old->isCommutable;
SU->hasPhysRegDefs = Old->hasPhysRegDefs;
SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
Old->isCloned = true;
return SU;
}
@ -172,9 +173,11 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
// Find all predecessors and successors of the group.
for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
if (N->isMachineOpcode() &&
TII->get(N->getMachineOpcode()).getImplicitDefs() &&
CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
SU->hasPhysRegDefs = true;
TII->get(N->getMachineOpcode()).getImplicitDefs()) {
SU->hasPhysRegClobbers = true;
if (CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
SU->hasPhysRegDefs = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
SDNode *OpN = N->getOperand(i).getNode();