From 39784e158a49c4920a3219fcab2841fe9250826c Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Mon, 4 Jan 2010 10:31:54 +0000 Subject: [PATCH] Fix invalid chain folding for memory variant of sdiv / udiv git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92472 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 52 +++++++++++----------- test/CodeGen/SystemZ/2010-01-04-DivMem.ll | 50 +++++++++++++++++++++ 2 files changed, 76 insertions(+), 26 deletions(-) create mode 100644 test/CodeGen/SystemZ/2010-01-04-DivMem.ll diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index d64611d7c07..f3189a8f408 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -643,16 +643,16 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { EVT ResVT; bool is32Bit = false; switch (NVT.getSimpleVT().SimpleTy) { - default: assert(0 && "Unsupported VT!"); - case MVT::i32: - Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; - ResVT = MVT::v2i64; - is32Bit = true; - break; - case MVT::i64: - Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m; - ResVT = MVT::v2i64; - break; + default: assert(0 && "Unsupported VT!"); + case MVT::i32: + Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; + ResVT = MVT::v2i64; + is32Bit = true; + break; + case MVT::i64: + Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m; + ResVT = MVT::v2i64; + break; } SDValue Tmp0, Tmp1, Tmp2; @@ -677,10 +677,10 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { SDValue DivVal = SDValue(Dividend, 0); if (foldedLoad) { SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; - Result = CurDAG->getMachineNode(MOpc, dl, ResVT, + Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other, Ops, array_lengthof(Ops)); // Update the chain. - ReplaceUses(N1.getValue(1), SDValue(Result, 0)); + ReplaceUses(N1.getValue(1), SDValue(Result, 1)); } else { Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1); } @@ -729,18 +729,18 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { bool is32Bit = false; switch (NVT.getSimpleVT().SimpleTy) { - default: assert(0 && "Unsupported VT!"); - case MVT::i32: - Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; - ClrOpc = SystemZ::MOV64Pr0_even; - ResVT = MVT::v2i32; - is32Bit = true; - break; - case MVT::i64: - Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; - ClrOpc = SystemZ::MOV128r0_even; - ResVT = MVT::v2i64; - break; + default: assert(0 && "Unsupported VT!"); + case MVT::i32: + Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; + ClrOpc = SystemZ::MOV64Pr0_even; + ResVT = MVT::v2i32; + is32Bit = true; + break; + case MVT::i64: + Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; + ClrOpc = SystemZ::MOV128r0_even; + ResVT = MVT::v2i64; + break; } SDValue Tmp0, Tmp1, Tmp2; @@ -767,10 +767,10 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { SDNode *Result; if (foldedLoad) { SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; - Result = CurDAG->getMachineNode(MOpc, dl,ResVT, + Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other, Ops, array_lengthof(Ops)); // Update the chain. - ReplaceUses(N1.getValue(1), SDValue(Result, 0)); + ReplaceUses(N1.getValue(1), SDValue(Result, 1)); } else { Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1); } diff --git a/test/CodeGen/SystemZ/2010-01-04-DivMem.ll b/test/CodeGen/SystemZ/2010-01-04-DivMem.ll new file mode 100644 index 00000000000..d730beca245 --- /dev/null +++ b/test/CodeGen/SystemZ/2010-01-04-DivMem.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s +target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16-n32:64" +target triple = "s390x-elf" + +@REGISTER = external global [10 x i32] ; <[10 x i32]*> [#uses=2] + +define void @DIVR_P(i32 signext %PRINT_EFFECT) nounwind { +entry: + %REG1 = alloca i32, align 4 ; [#uses=2] + %REG2 = alloca i32, align 4 ; [#uses=2] + %call = call signext i32 (...)* @FORMAT2(i32* %REG1, i32* %REG2) nounwind ; [#uses=0] + %tmp = load i32* %REG1 ; [#uses=1] + %idxprom = sext i32 %tmp to i64 ; [#uses=1] + %arrayidx = getelementptr inbounds [10 x i32]* @REGISTER, i64 0, i64 %idxprom ; [#uses=2] + %tmp1 = load i32* %arrayidx ; [#uses=2] + %tmp2 = load i32* %REG2 ; [#uses=1] + %idxprom3 = sext i32 %tmp2 to i64 ; [#uses=1] + %arrayidx4 = getelementptr inbounds [10 x i32]* @REGISTER, i64 0, i64 %idxprom3 ; [#uses=3] + %tmp5 = load i32* %arrayidx4 ; [#uses=3] + %cmp6 = icmp sgt i32 %tmp5, 8388607 ; [#uses=1] + %REG2_SIGN.0 = select i1 %cmp6, i32 -1, i32 1 ; [#uses=2] + %cmp10 = icmp eq i32 %REG2_SIGN.0, 1 ; [#uses=1] + %not.cmp = icmp slt i32 %tmp1, 8388608 ; [#uses=2] + %or.cond = and i1 %cmp10, %not.cmp ; [#uses=1] + br i1 %or.cond, label %if.then13, label %if.end25 + +if.then13: ; preds = %entry + %div = sdiv i32 %tmp5, %tmp1 ; [#uses=2] + store i32 %div, i32* %arrayidx4 + br label %if.end25 + +if.end25: ; preds = %if.then13, %entry + %tmp35 = phi i32 [ %div, %if.then13 ], [ %tmp5, %entry ] ; [#uses=1] + %cmp27 = icmp eq i32 %REG2_SIGN.0, -1 ; [#uses=1] + %or.cond46 = and i1 %cmp27, %not.cmp ; [#uses=1] + br i1 %or.cond46, label %if.then31, label %if.end45 + +if.then31: ; preds = %if.end25 + %sub = sub i32 16777216, %tmp35 ; [#uses=1] + %tmp39 = load i32* %arrayidx ; [#uses=1] + %div40 = udiv i32 %sub, %tmp39 ; [#uses=1] + %sub41 = sub i32 16777216, %div40 ; [#uses=1] + store i32 %sub41, i32* %arrayidx4 + ret void + +if.end45: ; preds = %if.end25 + ret void +} + +declare signext i32 @FORMAT2(...)