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R600/SI: Use -verify-machineinstrs for most tests

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We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-10-10 17:11:46 +00:00
parent 0f9eaaa8aa
commit 3986785046
84 changed files with 86 additions and 86 deletions
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2
test/CodeGen/R600/128bit-kernel-args.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @v4i32_kernel_arg ; R600-CHECK: @v4i32_kernel_arg
; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y ; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y

2
test/CodeGen/R600/32-bit-local-address-space.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and ; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
; the global address space(1) uses 64-bit pointers. These tests check to make sure ; the global address space(1) uses 64-bit pointers. These tests check to make sure

2
test/CodeGen/R600/64bit-kernel-args.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; SI-CHECK: @f64_kernel_arg ; SI-CHECK: @f64_kernel_arg
; SI-CHECK-DAG: S_LOAD_DWORDX2 SGPR{{[0-9]}}_SGPR{{[0-9]}}, SGPR0_SGPR1, 9 ; SI-CHECK-DAG: S_LOAD_DWORDX2 SGPR{{[0-9]}}_SGPR{{[0-9]}}, SGPR0_SGPR1, 9

2
test/CodeGen/R600/add.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @test2 ;EG-CHECK: @test2
;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/and.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @test2 ;EG-CHECK: @test2
;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/atomic_load_add.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK-LABEL: @atomic_add_local ; R600-CHECK-LABEL: @atomic_add_local
; R600-CHECK: LDS_ADD * ; R600-CHECK: LDS_ADD *

2
test/CodeGen/R600/atomic_load_sub.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK-LABEL: @atomic_sub_local ; R600-CHECK-LABEL: @atomic_sub_local
; R600-CHECK: LDS_SUB * ; R600-CHECK: LDS_SUB *

2
test/CodeGen/R600/bfi_int.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; BFI_INT Definition pattern from ISA docs ; BFI_INT Definition pattern from ISA docs
; (y & x) | (z & ~x) ; (y & x) | (z & ~x)

2
test/CodeGen/R600/bitcast.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
; This test just checks that the compiler doesn't crash. ; This test just checks that the compiler doesn't crash.
; CHECK-LABEL: @v32i8_to_v8i32 ; CHECK-LABEL: @v32i8_to_v8i32

2
test/CodeGen/R600/build_vector.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @build_vector2 ; R600-CHECK: @build_vector2
; R600-CHECK: MOV ; R600-CHECK: MOV

4
test/CodeGen/R600/elf.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG-CHECK %s
; ELF-CHECK: Format: ELF32 ; ELF-CHECK: Format: ELF32
; ELF-CHECK: Name: .AMDGPU.config ; ELF-CHECK: Name: .AMDGPU.config

2
test/CodeGen/R600/fabs.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; DAGCombiner will transform: ; DAGCombiner will transform:
; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF)) ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))

2
test/CodeGen/R600/fadd.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @fadd_f32 ; R600-CHECK: @fadd_f32
; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W

2
test/CodeGen/R600/fadd64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fadd_f64 ; CHECK: @fadd_f64
; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}} ; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}

2
test/CodeGen/R600/fcmp64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @flt_f64 ; CHECK: @flt_f64
; CHECK: V_CMP_LT_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}} ; CHECK: V_CMP_LT_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}

2
test/CodeGen/R600/fconst64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fconst_f64 ; CHECK: @fconst_f64
; CHECK: V_MOV_B32_e32 {{VGPR[0-9]+}}, 0.000000e+00 ; CHECK: V_MOV_B32_e32 {{VGPR[0-9]+}}, 0.000000e+00

2
test/CodeGen/R600/fdiv.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; These tests check that fdiv is expanded correctly and also test that the ; These tests check that fdiv is expanded correctly and also test that the
; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate ; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate

2
test/CodeGen/R600/fdiv64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fdiv_f64 ; CHECK: @fdiv_f64
; CHECK: V_RCP_F64_e32 {{VGPR[0-9]+_VGPR[0-9]+}} ; CHECK: V_RCP_F64_e32 {{VGPR[0-9]+_VGPR[0-9]+}}

2
test/CodeGen/R600/fma.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
; CHECK: @fma_f32 ; CHECK: @fma_f32
; CHECK: V_FMA_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ; CHECK: V_FMA_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}

2
test/CodeGen/R600/fmul.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @fmul_f32 ; R600-CHECK: @fmul_f32
; R600-CHECK: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W ; R600-CHECK: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W

2
test/CodeGen/R600/fmul64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fmul_f64 ; CHECK: @fmul_f64
; CHECK: V_MUL_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}} ; CHECK: V_MUL_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}

2
test/CodeGen/R600/fmuladd.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
; CHECK: @fmuladd_f32 ; CHECK: @fmuladd_f32
; CHECK: V_MAD_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ; CHECK: V_MAD_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}

2
test/CodeGen/R600/fp64_to_sint.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
; CHECK: @fp64_to_sint ; CHECK: @fp64_to_sint
; CHECK: V_CVT_I32_F64_e32 ; CHECK: V_CVT_I32_F64_e32

2
test/CodeGen/R600/fp_to_sint.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @fp_to_sint_v2i32 ; R600-CHECK: @fp_to_sint_v2i32
; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}

2
test/CodeGen/R600/fp_to_uint.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @fp_to_uint_v2i32 ; R600-CHECK: @fp_to_uint_v2i32
; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}

2
test/CodeGen/R600/fpext.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
; CHECK: @fpext ; CHECK: @fpext
; CHECK: V_CVT_F64_F32_e32 ; CHECK: V_CVT_F64_F32_e32

2
test/CodeGen/R600/fptrunc.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
; CHECK: @fptrunc ; CHECK: @fptrunc
; CHECK: V_CVT_F32_F64_e32 ; CHECK: V_CVT_F32_F64_e32

2
test/CodeGen/R600/fsqrt.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fsqrt_f32 ; CHECK: @fsqrt_f32
; CHECK: V_SQRT_F32_e32 {{VGPR[0-9]+, VGPR[0-9]+}} ; CHECK: V_SQRT_F32_e32 {{VGPR[0-9]+, VGPR[0-9]+}}

2
test/CodeGen/R600/fsub.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @fsub_f32 ; R600-CHECK: @fsub_f32
; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W

2
test/CodeGen/R600/fsub64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fsub_f64 ; CHECK: @fsub_f64
; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}, 0, 0, 0, 0, 2 ; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}, 0, 0, 0, 0, 2

2
test/CodeGen/R600/imm.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
; Use a 64-bit value with lo bits that can be represented as an inline constant ; Use a 64-bit value with lo bits that can be represented as an inline constant
; CHECK: @i64_imm_inline_lo ; CHECK: @i64_imm_inline_lo

2
test/CodeGen/R600/indirect-addressing-si.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
; Tests for indirect addressing on SI, which is implemented using dynamic ; Tests for indirect addressing on SI, which is implemented using dynamic
; indexing of vectors. ; indexing of vectors.

2
test/CodeGen/R600/llvm.AMDGPU.imax.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_MAX_I32_e32 ;CHECK: V_MAX_I32_e32

2
test/CodeGen/R600/llvm.AMDGPU.imin.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_MIN_I32_e32 ;CHECK: V_MIN_I32_e32

2
test/CodeGen/R600/llvm.AMDGPU.trunc.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; R600-CHECK: @amdgpu_trunc ; R600-CHECK: @amdgpu_trunc
; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z

2
test/CodeGen/R600/llvm.AMDGPU.umax.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_MAX_U32_e32 ;CHECK: V_MAX_U32_e32

2
test/CodeGen/R600/llvm.AMDGPU.umin.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_MIN_U32_e32 ;CHECK: V_MIN_U32_e32

2
test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: S_MOV_B32 ;CHECK: S_MOV_B32
;CHECK-NEXT: V_INTERP_MOV_F32 ;CHECK-NEXT: V_INTERP_MOV_F32

2
test/CodeGen/R600/llvm.SI.imageload.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK-DAG: IMAGE_LOAD {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1 ;CHECK-DAG: IMAGE_LOAD {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1
;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0 ;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0

2
test/CodeGen/R600/llvm.SI.resinfo.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: IMAGE_GET_RESINFO {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1 ;CHECK: IMAGE_GET_RESINFO {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1
;CHECK: IMAGE_GET_RESINFO {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0 ;CHECK: IMAGE_GET_RESINFO {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0

2
test/CodeGen/R600/llvm.SI.sample.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15 ;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3 ;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3

2
test/CodeGen/R600/llvm.SI.sampled.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15 ;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3 ;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3

2
test/CodeGen/R600/llvm.SI.tbuffer.store.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK_LABEL: @test1 ;CHECK_LABEL: @test1
;CHECK: TBUFFER_STORE_FORMAT_XYZW {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 32, -1, 0, -1, 0, 14, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0 ;CHECK: TBUFFER_STORE_FORMAT_XYZW {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 32, -1, 0, -1, 0, 14, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0

2
test/CodeGen/R600/llvm.SI.tid.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_MBCNT_LO_U32_B32_e64 ;CHECK: V_MBCNT_LO_U32_B32_e64
;CHECK: V_MBCNT_HI_U32_B32_e32 ;CHECK: V_MBCNT_HI_U32_B32_e32

2
test/CodeGen/R600/llvm.floor.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @f32 ; R600-CHECK: @f32
; R600-CHECK: FLOOR ; R600-CHECK: FLOOR

2
test/CodeGen/R600/llvm.rint.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @f32 ; R600-CHECK: @f32
; R600-CHECK: RNDNE ; R600-CHECK: RNDNE

2
test/CodeGen/R600/load.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;===------------------------------------------------------------------------===; ;===------------------------------------------------------------------------===;
; GLOBAL ADDRESS SPACE ; GLOBAL ADDRESS SPACE

2
test/CodeGen/R600/load.vec.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; load a v2i32 value from the global address space. ; load a v2i32 value from the global address space.
; EG-CHECK: @load_v2i32 ; EG-CHECK: @load_v2i32

2
test/CodeGen/R600/load64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; load a f64 value from the global address space. ; load a f64 value from the global address space.
; CHECK: @load_f64 ; CHECK: @load_f64

2
test/CodeGen/R600/local-memory-two-objects.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
@local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 @local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
@local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 @local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4

2
test/CodeGen/R600/local-memory.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
@local_memory.local_mem = internal addrspace(3) unnamed_addr global [16 x i32] zeroinitializer, align 4 @local_memory.local_mem = internal addrspace(3) unnamed_addr global [16 x i32] zeroinitializer, align 4

2
test/CodeGen/R600/lshl.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1 ;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1

2
test/CodeGen/R600/lshr.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]}}, SGPR{{[0-9]}}, 1 ;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]}}, SGPR{{[0-9]}}, 1

2
test/CodeGen/R600/mad_int24.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; EG-CHECK: @i32_mad24 ; EG-CHECK: @i32_mad24
; Signed 24-bit multiply is not supported on pre-Cayman GPUs. ; Signed 24-bit multiply is not supported on pre-Cayman GPUs.

2
test/CodeGen/R600/mad_uint24.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; EG-CHECK: @u32_mad24 ; EG-CHECK: @u32_mad24
; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X

2
test/CodeGen/R600/mul.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; mul24 and mad24 are affected ; mul24 and mad24 are affected

2
test/CodeGen/R600/mul_int24.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; EG-CHECK: @i32_mul24 ; EG-CHECK: @i32_mul24
; Signed 24-bit multiply is not supported on pre-Cayman GPUs. ; Signed 24-bit multiply is not supported on pre-Cayman GPUs.

2
test/CodeGen/R600/mul_uint24.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; EG-CHECK: @u32_mul24 ; EG-CHECK: @u32_mul24
; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W ; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W

2
test/CodeGen/R600/mulhu.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_MOV_B32_e32 VGPR{{[0-9]+}}, -1431655765 ;CHECK: V_MOV_B32_e32 VGPR{{[0-9]+}}, -1431655765
;CHECK: V_MUL_HI_U32 VGPR0, {{[SV]GPR[0-9]+}}, {{VGPR[0-9]+}} ;CHECK: V_MUL_HI_U32 VGPR0, {{[SV]GPR[0-9]+}}, {{VGPR[0-9]+}}

2
test/CodeGen/R600/or.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; EG-CHECK: @or_v2i32 ; EG-CHECK: @or_v2i32
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

4
test/CodeGen/R600/rotr.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; R600-CHECK: @rotr ; R600-CHECK: @rotr
; R600-CHECK: BIT_ALIGN_INT ; R600-CHECK: BIT_ALIGN_INT

2
test/CodeGen/R600/seto.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0 ;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0

2
test/CodeGen/R600/setuo.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0 ;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0

2
test/CodeGen/R600/sgpr-copy.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
; This test checks that no VGPR to SGPR copies are created by the register ; This test checks that no VGPR to SGPR copies are created by the register
; allocator. ; allocator.

2
test/CodeGen/R600/shl.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @shl_v2i32 ;EG-CHECK: @shl_v2i32
;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/short-args.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; EG-CHECK: @i8_arg ; EG-CHECK: @i8_arg
; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z

2
test/CodeGen/R600/si-lod-bias.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
; This shader has the potential to generated illeagal VGPR to SGPR copies if ; This shader has the potential to generated illeagal VGPR to SGPR copies if
; the wrong register class is used for the REG_SEQUENCE instructions. ; the wrong register class is used for the REG_SEQUENCE instructions.

2
test/CodeGen/R600/si-vector-hang.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
; CHECK: @test_8_min_char ; CHECK: @test_8_min_char
; CHECK: BUFFER_STORE_BYTE ; CHECK: BUFFER_STORE_BYTE

2
test/CodeGen/R600/sign_extend.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
; CHECK: V_ASHR ; CHECK: V_ASHR
define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {

2
test/CodeGen/R600/sint_to_fp.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @sint_to_fp_v2i32 ; R600-CHECK: @sint_to_fp_v2i32
; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W ; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W

2
test/CodeGen/R600/sint_to_fp64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
; CHECK: @sint_to_fp64 ; CHECK: @sint_to_fp64
; CHECK: V_CVT_F64_I32_e32 ; CHECK: V_CVT_F64_I32_e32

2
test/CodeGen/R600/sra.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @ashr_v2i32 ;EG-CHECK: @ashr_v2i32
;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/srl.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @lshr_v2i32 ;EG-CHECK: @lshr_v2i32
;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/store.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;===------------------------------------------------------------------------===; ;===------------------------------------------------------------------------===;
; Global Address Space ; Global Address Space

2
test/CodeGen/R600/sub.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @test2 ;EG-CHECK: @test2
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/trunc.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s

2
test/CodeGen/R600/udiv.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;The code generated by udiv is long and complex and may frequently change. ;The code generated by udiv is long and complex and may frequently change.
;The goal of this test is to make sure the ISel doesn't fail when it gets ;The goal of this test is to make sure the ISel doesn't fail when it gets

2
test/CodeGen/R600/uint_to_fp.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @uint_to_fp_v2i32 ; R600-CHECK: @uint_to_fp_v2i32
; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W ; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W

2
test/CodeGen/R600/urecip.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_RCP_IFLAG_F32_e32 ;CHECK: V_RCP_IFLAG_F32_e32

2
test/CodeGen/R600/urem.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;The code generated by urem is long and complex and may frequently change. ;The code generated by urem is long and complex and may frequently change.
;The goal of this test is to make sure the ISel doesn't fail when it gets ;The goal of this test is to make sure the ISel doesn't fail when it gets

2
test/CodeGen/R600/vselect.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @test_select_v2i32 ;EG-CHECK: @test_select_v2i32
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/work-item-intrinsics.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; R600-CHECK: @ngroups_x ; R600-CHECK: @ngroups_x
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]

2
test/CodeGen/R600/xor.ll
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@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
;EG-CHECK: @xor_v2i32 ;EG-CHECK: @xor_v2i32
;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

2
test/CodeGen/R600/zero_extend.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @test ; R600-CHECK: @test
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW ; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW