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[DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles into a single shuffle if the resulting mask is legal.
This patch teaches the DAGCombiner how to fold shuffles according to the following new rules: 1. shuffle(shuffle(x, y), undef) -> x 2. shuffle(shuffle(x, y), undef) -> y 3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef) 4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef) The backend avoids to combine shuffles according to rules 3. and 4. if the resulting shuffle does not have a legal mask. This is to avoid introducing illegal shuffles that are potentially expanded into a sub-optimal sequence of target specific dag nodes during vector legalization. Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers the new rules when combining shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212748 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
60079c18bc
commit
3996e5290a
@ -10677,17 +10677,12 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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}
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// If this shuffle node is simply a swizzle of another shuffle node,
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// and it reverses the swizzle of the previous shuffle then we can
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// optimize shuffle(shuffle(x, undef), undef) -> x.
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// then try to simplify it.
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if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
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N1.getOpcode() == ISD::UNDEF) {
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ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
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// Shuffle nodes can only reverse shuffles with a single non-undef value.
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if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
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return SDValue();
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// The incoming shuffle must be of the same type as the result of the
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// current shuffle.
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assert(OtherSV->getOperand(0).getValueType() == VT &&
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@ -10704,27 +10699,69 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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Idx = OtherSV->getMaskElt(Idx);
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Mask.push_back(Idx);
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}
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bool CommuteOperands = false;
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if (N0.getOperand(1).getOpcode() != ISD::UNDEF) {
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// To be valid, the combine shuffle mask should only reference elements
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// from one of the two vectors in input to the inner shufflevector.
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bool IsValidMask = true;
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for (unsigned i = 0; i != NumElts && IsValidMask; ++i)
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// See if the combined mask only reference undefs or elements coming
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// from the first shufflevector operand.
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IsValidMask = Mask[i] < 0 || (unsigned)Mask[i] < NumElts;
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if (!IsValidMask) {
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IsValidMask = true;
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for (unsigned i = 0; i != NumElts && IsValidMask; ++i)
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// Check that all the elements come from the second shuffle operand.
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IsValidMask = Mask[i] < 0 || (unsigned)Mask[i] >= NumElts;
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CommuteOperands = IsValidMask;
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}
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// Early exit if the combined shuffle mask is not valid.
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if (!IsValidMask)
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return SDValue();
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}
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// See if this pair of shuffles can be safely folded according to either
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// of the following rules:
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// shuffle(shuffle(x, y), undef) -> x
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// shuffle(shuffle(x, undef), undef) -> x
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// shuffle(shuffle(x, y), undef) -> y
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bool IsIdentityMask = true;
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unsigned BaseMaskIndex = CommuteOperands ? NumElts : 0;
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for (unsigned i = 0; i != NumElts && IsIdentityMask; ++i) {
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// Skip Undefs.
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if (Mask[i] < 0)
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continue;
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// The combined shuffle must map each index to itself.
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IsIdentityMask = (unsigned)Mask[i] == i;
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IsIdentityMask = (unsigned)Mask[i] == i + BaseMaskIndex;
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}
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if (IsIdentityMask)
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// optimize shuffle(shuffle(x, undef), undef) -> x.
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if (IsIdentityMask) {
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if (CommuteOperands)
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// optimize shuffle(shuffle(x, y), undef) -> y.
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return OtherSV->getOperand(1);
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// optimize shuffle(shuffle(x, undef), undef) -> x
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// optimize shuffle(shuffle(x, y), undef) -> x
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return OtherSV->getOperand(0);
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}
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// It may still be beneficial to combine the two shuffles if the
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// resulting shuffle is legal.
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// shuffle(shuffle(x, undef, M1), undef, M2) -> shuffle(x, undef, M3).
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if (TLI.isShuffleMaskLegal(Mask, VT))
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return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0), N1,
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if (TLI.isShuffleMaskLegal(Mask, VT)) {
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if (!CommuteOperands)
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// shuffle(shuffle(x, undef, M1), undef, M2) -> shuffle(x, undef, M3).
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// shuffle(shuffle(x, y, M1), undef, M2) -> shuffle(x, undef, M3)
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return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0), N1,
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&Mask[0]);
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// shuffle(shuffle(x, y, M1), undef, M2) -> shuffle(undef, y, M3)
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return DAG.getVectorShuffle(VT, SDLoc(N), N1, N0->getOperand(1),
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&Mask[0]);
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}
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}
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return SDValue();
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164
test/CodeGen/X86/combine-vec-shuffle-2.ll
Normal file
164
test/CodeGen/X86/combine-vec-shuffle-2.ll
Normal file
@ -0,0 +1,164 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Check that DAGCombiner correctly folds the following pairs of shuffles
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; using the following rules:
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; 1. shuffle(shuffle(x, y), undef) -> x
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; 2. shuffle(shuffle(x, y), undef) -> y
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; 3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
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; 4. shuffle(shuffle(x, y), undef) -> shuffle(undef, y)
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;
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; Rules 3. and 4. are used only if the resulting shuffle mask is legal.
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define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test1
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; Mask: [3,0,0,1]
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; CHECK: pshufd $67
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; CHECK-NEXT: ret
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define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test2
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; Mask: [2,0,0,3]
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; CHECK: pshufd $-62
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; CHECK-NEXT: ret
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define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test3
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; Mask: [2,0,0,3]
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; CHECK: pshufd $-62
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; CHECK-NEXT: ret
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define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test4
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; Mask: [0,0,0,1]
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; CHECK: pshufd $64
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; CHECK-NEXT: ret
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define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test5
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; Mask: [1,1]
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; CHECK: movhlps
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; CHECK-NEXT: ret
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define <4 x i32> @test6(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test6
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; Mask: [2,0,0,0]
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; CHECK: pshufd $2
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; CHECK-NEXT: ret
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define <4 x i32> @test7(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test7
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; Mask: [0,2,0,2]
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; CHECK: pshufd $-120
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; CHECK-NEXT: ret
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define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test8
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; Mask: [1,0,3,0]
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; CHECK: pshufd $49
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; CHECK-NEXT: ret
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define <4 x i32> @test9(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test9
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; Mask: [1,3,0,2]
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; CHECK: pshufd $-115
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; CHECK-NEXT: ret
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define <4 x i32> @test10(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test10
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; Mask: [1,0,1,0]
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; CHECK: pshufd $17
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; CHECK-NEXT: ret
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define <4 x i32> @test11(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test11
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; Mask: [1,0,2,1]
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; CHECK: pshufd $97
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; CHECK-NEXT: ret
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define <4 x i32> @test12(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test12
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; Mask: [0,0,0,0]
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; CHECK: pshufd $0
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; CHECK-NEXT: ret
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; The following pair of shuffles is folded into vector %A.
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define <4 x i32> @test13(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: pshufd
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; CHECK: ret
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; The following pair of shuffles is folded into vector %B.
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define <4 x i32> @test14(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: pshufd
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; CHECK: ret
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@ -33,7 +33,9 @@ entry:
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define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
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entry:
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; CHECK-LABEL: shuf3:
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; CHECK: shufps
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; CHECK-NOT: movlhps
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; CHECK-NOT: shufps
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; CHECK: pshufd
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%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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