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Use MCPhysReg for RegisterClassInfo allocation orders.

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This saves a bit of memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-11-29 03:34:17 +00:00
parent e26e8a64ab
commit 39b5c0c049
7 changed files with 20 additions and 18 deletions
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6
include/llvm/CodeGen/RegisterClassInfo.h
View File

@ -29,10 +29,10 @@ class RegisterClassInfo {
unsigned Tag;
unsigned NumRegs;
bool ProperSubClass;
OwningArrayPtr<unsigned> Order;
OwningArrayPtr<MCPhysReg> Order;
RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {}
operator ArrayRef<unsigned>() const {
operator ArrayRef<MCPhysReg>() const {
return makeArrayRef(Order.get(), NumRegs);
}
};
@ -84,7 +84,7 @@ public:
/// getOrder - Returns the preferred allocation order for RC. The order
/// contains no reserved registers, and registers that alias callee saved
/// registers come last.
ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const {
ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
return get(RC);
}

2
lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -616,7 +616,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
const TargetRegisterClass *SuperRC =
TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
if (Order.empty()) {
DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
return false;

6
lib/CodeGen/AllocationOrder.cpp
View File

@ -42,7 +42,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
if (HintPair.first) {
const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
// The remaining allocation order may depend on the hint.
ArrayRef<uint16_t> Order =
ArrayRef<MCPhysReg> Order =
TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
VRM.getMachineFunction());
if (Order.empty())
@ -50,7 +50,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
// Copy the allocation order with reserved registers removed.
OwnedBegin = true;
unsigned *P = new unsigned[Order.size()];
MCPhysReg *P = new MCPhysReg[Order.size()];
Begin = P;
for (unsigned i = 0; i != Order.size(); ++i)
if (!MRI.isReserved(Order[i]))
@ -63,7 +63,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
} else {
// If there is no hint or just a normal hint, use the cached allocation
// order from RegisterClassInfo.
ArrayRef<unsigned> O = RCI.getOrder(RC);
ArrayRef<MCPhysReg> O = RCI.getOrder(RC);
Begin = O.begin();
End = O.end();
}

8
lib/CodeGen/AllocationOrder.h
View File

@ -17,15 +17,17 @@
#ifndef LLVM_CODEGEN_ALLOCATIONORDER_H
#define LLVM_CODEGEN_ALLOCATIONORDER_H
#include "llvm/MC/MCRegisterInfo.h"
namespace llvm {
class RegisterClassInfo;
class VirtRegMap;
class AllocationOrder {
const unsigned *Begin;
const unsigned *End;
const unsigned *Pos;
const MCPhysReg *Begin;
const MCPhysReg *End;
const MCPhysReg *Pos;
const RegisterClassInfo &RCI;
unsigned Hint;
bool OwnedBegin;

2
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -378,7 +378,7 @@ CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin,
unsigned LastNewReg,
const TargetRegisterClass *RC)
{
ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
for (unsigned i = 0; i != Order.size(); ++i) {
unsigned NewReg = Order[i];
// Don't replace a register with itself.

6
lib/CodeGen/RegAllocFast.cpp
View File

@ -527,10 +527,10 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
}
}
ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
// First try to find a completely free register.
for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
unsigned PhysReg = *I;
if (PhysRegState[PhysReg] == regFree && !UsedInInstr.count(PhysReg)) {
assignVirtToPhysReg(*LRI, PhysReg);
@ -542,7 +542,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
<< RC->getName() << "\n");
unsigned BestReg = 0, BestCost = spillImpossible;
for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
unsigned Cost = calcSpillCost(*I);
DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
DEBUG(dbgs() << "\tCost: " << Cost << "\n");

8
lib/CodeGen/RegisterClassInfo.cpp
View File

@ -44,7 +44,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
}
// Does this MF have different CSRs?
const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
if (Update || CSR != CalleeSaved) {
// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
// overlapping CSR.
@ -79,14 +79,14 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
unsigned NumRegs = RC->getNumRegs();
if (!RCI.Order)
RCI.Order.reset(new unsigned[NumRegs]);
RCI.Order.reset(new MCPhysReg[NumRegs]);
unsigned N = 0;
SmallVector<unsigned, 16> CSRAlias;
SmallVector<MCPhysReg, 16> CSRAlias;
// FIXME: Once targets reserve registers instead of removing them from the
// allocation order, we can simply use begin/end here.
ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF);
ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
for (unsigned i = 0; i != RawOrder.size(); ++i) {
unsigned PhysReg = RawOrder[i];
// Remove reserved registers from the allocation order.