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Use MCPhysReg for RegisterClassInfo allocation orders.
This saves a bit of memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -29,10 +29,10 @@ class RegisterClassInfo {
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unsigned Tag;
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unsigned Tag;
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unsigned NumRegs;
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unsigned NumRegs;
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bool ProperSubClass;
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bool ProperSubClass;
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OwningArrayPtr<unsigned> Order;
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OwningArrayPtr<MCPhysReg> Order;
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RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {}
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RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {}
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operator ArrayRef<unsigned>() const {
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operator ArrayRef<MCPhysReg>() const {
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return makeArrayRef(Order.get(), NumRegs);
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return makeArrayRef(Order.get(), NumRegs);
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}
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}
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};
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};
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@ -84,7 +84,7 @@ public:
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/// getOrder - Returns the preferred allocation order for RC. The order
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/// getOrder - Returns the preferred allocation order for RC. The order
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/// contains no reserved registers, and registers that alias callee saved
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/// contains no reserved registers, and registers that alias callee saved
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/// registers come last.
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/// registers come last.
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ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const {
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ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
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return get(RC);
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return get(RC);
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}
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}
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@ -616,7 +616,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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const TargetRegisterClass *SuperRC =
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const TargetRegisterClass *SuperRC =
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TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
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TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
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ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
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ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
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if (Order.empty()) {
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if (Order.empty()) {
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DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
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DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
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return false;
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return false;
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@ -42,7 +42,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
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if (HintPair.first) {
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if (HintPair.first) {
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const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
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const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
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// The remaining allocation order may depend on the hint.
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// The remaining allocation order may depend on the hint.
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ArrayRef<uint16_t> Order =
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ArrayRef<MCPhysReg> Order =
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TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
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TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
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VRM.getMachineFunction());
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VRM.getMachineFunction());
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if (Order.empty())
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if (Order.empty())
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@ -50,7 +50,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
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// Copy the allocation order with reserved registers removed.
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// Copy the allocation order with reserved registers removed.
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OwnedBegin = true;
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OwnedBegin = true;
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unsigned *P = new unsigned[Order.size()];
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MCPhysReg *P = new MCPhysReg[Order.size()];
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Begin = P;
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Begin = P;
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for (unsigned i = 0; i != Order.size(); ++i)
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for (unsigned i = 0; i != Order.size(); ++i)
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if (!MRI.isReserved(Order[i]))
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if (!MRI.isReserved(Order[i]))
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@ -63,7 +63,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
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} else {
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} else {
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// If there is no hint or just a normal hint, use the cached allocation
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// If there is no hint or just a normal hint, use the cached allocation
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// order from RegisterClassInfo.
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// order from RegisterClassInfo.
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ArrayRef<unsigned> O = RCI.getOrder(RC);
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ArrayRef<MCPhysReg> O = RCI.getOrder(RC);
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Begin = O.begin();
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Begin = O.begin();
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End = O.end();
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End = O.end();
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}
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}
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@ -17,15 +17,17 @@
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#ifndef LLVM_CODEGEN_ALLOCATIONORDER_H
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#ifndef LLVM_CODEGEN_ALLOCATIONORDER_H
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#define LLVM_CODEGEN_ALLOCATIONORDER_H
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#define LLVM_CODEGEN_ALLOCATIONORDER_H
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#include "llvm/MC/MCRegisterInfo.h"
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namespace llvm {
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namespace llvm {
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class RegisterClassInfo;
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class RegisterClassInfo;
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class VirtRegMap;
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class VirtRegMap;
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class AllocationOrder {
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class AllocationOrder {
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const unsigned *Begin;
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const MCPhysReg *Begin;
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const unsigned *End;
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const MCPhysReg *End;
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const unsigned *Pos;
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const MCPhysReg *Pos;
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const RegisterClassInfo &RCI;
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const RegisterClassInfo &RCI;
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unsigned Hint;
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unsigned Hint;
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bool OwnedBegin;
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bool OwnedBegin;
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@ -378,7 +378,7 @@ CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin,
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unsigned LastNewReg,
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unsigned LastNewReg,
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const TargetRegisterClass *RC)
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const TargetRegisterClass *RC)
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{
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{
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ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
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ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
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for (unsigned i = 0; i != Order.size(); ++i) {
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for (unsigned i = 0; i != Order.size(); ++i) {
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unsigned NewReg = Order[i];
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unsigned NewReg = Order[i];
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// Don't replace a register with itself.
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// Don't replace a register with itself.
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@ -527,10 +527,10 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
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}
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}
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}
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}
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ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
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ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
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// First try to find a completely free register.
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// First try to find a completely free register.
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for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
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for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
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unsigned PhysReg = *I;
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unsigned PhysReg = *I;
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if (PhysRegState[PhysReg] == regFree && !UsedInInstr.count(PhysReg)) {
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if (PhysRegState[PhysReg] == regFree && !UsedInInstr.count(PhysReg)) {
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assignVirtToPhysReg(*LRI, PhysReg);
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assignVirtToPhysReg(*LRI, PhysReg);
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@ -542,7 +542,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
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<< RC->getName() << "\n");
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<< RC->getName() << "\n");
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unsigned BestReg = 0, BestCost = spillImpossible;
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unsigned BestReg = 0, BestCost = spillImpossible;
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for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
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for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
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unsigned Cost = calcSpillCost(*I);
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unsigned Cost = calcSpillCost(*I);
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DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
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DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
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DEBUG(dbgs() << "\tCost: " << Cost << "\n");
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DEBUG(dbgs() << "\tCost: " << Cost << "\n");
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@ -44,7 +44,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
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}
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}
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// Does this MF have different CSRs?
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// Does this MF have different CSRs?
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const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
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const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
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if (Update || CSR != CalleeSaved) {
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if (Update || CSR != CalleeSaved) {
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// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
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// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
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// overlapping CSR.
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// overlapping CSR.
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@ -79,14 +79,14 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
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unsigned NumRegs = RC->getNumRegs();
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unsigned NumRegs = RC->getNumRegs();
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if (!RCI.Order)
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if (!RCI.Order)
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RCI.Order.reset(new unsigned[NumRegs]);
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RCI.Order.reset(new MCPhysReg[NumRegs]);
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unsigned N = 0;
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unsigned N = 0;
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SmallVector<unsigned, 16> CSRAlias;
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SmallVector<MCPhysReg, 16> CSRAlias;
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// FIXME: Once targets reserve registers instead of removing them from the
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// FIXME: Once targets reserve registers instead of removing them from the
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// allocation order, we can simply use begin/end here.
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// allocation order, we can simply use begin/end here.
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ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF);
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ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
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for (unsigned i = 0; i != RawOrder.size(); ++i) {
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for (unsigned i = 0; i != RawOrder.size(); ++i) {
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unsigned PhysReg = RawOrder[i];
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unsigned PhysReg = RawOrder[i];
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// Remove reserved registers from the allocation order.
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// Remove reserved registers from the allocation order.
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