mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-20 16:17:38 +00:00
Update Transforms tests to use CHECK-LABEL for easier debugging. No functionality change.
This update was done with the following bash script:
find test/Transforms -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_]*\):\( *\)@$FUNC\([( ]*\)\$/;\1\2-LABEL:\3@$FUNC(/g" $TEMP
done
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186268 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -5,7 +5,7 @@ declare i32 @f2()
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declare void @f3()
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define i32 @test1(i1 %cond) {
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; CHECK: @test1
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; CHECK-LABEL: @test1(
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br i1 %cond, label %T1, label %F1
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@@ -37,7 +37,7 @@ F2:
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;; cond is known false on Entry -> F1 edge!
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define i32 @test2(i1 %cond) {
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; CHECK: @test2
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; CHECK-LABEL: @test2(
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Entry:
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br i1 %cond, label %T1, label %F1
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@@ -62,7 +62,7 @@ F2:
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; Undef handling.
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define i32 @test3(i1 %cond) {
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; CHECK: @test3
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: T1:
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; CHECK-NEXT: ret i32 42
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br i1 undef, label %T1, label %F1
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@@ -75,7 +75,7 @@ F1:
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}
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define i32 @test4(i1 %cond, i1 %cond2) {
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; CHECK: @test4
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; CHECK-LABEL: @test4(
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br i1 %cond, label %T1, label %F1
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@@ -108,7 +108,7 @@ F2:
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;; This tests that the branch in 'merge' can be cloned up into T1.
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define i32 @test5(i1 %cond, i1 %cond2) {
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; CHECK: @test5
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; CHECK-LABEL: @test5(
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br i1 %cond, label %T1, label %F1
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@@ -144,7 +144,7 @@ F2:
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define i32 @test6(i32 %A) {
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; CHECK: @test6
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; CHECK-LABEL: @test6(
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%tmp455 = icmp eq i32 %A, 42
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br i1 %tmp455, label %BB1, label %BB2
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@@ -180,7 +180,7 @@ BB4:
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;; rdar://7367025
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define i32 @test7(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test7
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; CHECK-LABEL: @test7(
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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@@ -213,7 +213,7 @@ F2:
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declare i1 @test8a()
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define i32 @test8b(i1 %cond, i1 %cond2) {
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; CHECK: @test8b
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; CHECK-LABEL: @test8b(
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T0:
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%A = call i1 @test8a()
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br i1 %A, label %T1, label %F1
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@@ -255,7 +255,7 @@ Y:
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;;; Verify that we can handle constraint propagation through "xor x, 1".
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define i32 @test9(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test9
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; CHECK-LABEL: @test9(
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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@@ -298,7 +298,7 @@ declare void @test10f3()
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;; Non-local condition threading.
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define i32 @test10g(i1 %cond) {
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; CHECK: @test10g
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; CHECK-LABEL: @test10g(
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; CHECK-NEXT: br i1 %cond, label %T2, label %F2
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br i1 %cond, label %T1, label %F1
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@@ -329,7 +329,7 @@ F2:
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; Impossible conditional constraints should get threaded. BB3 is dead here.
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define i32 @test11(i32 %A) {
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; CHECK: @test11
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; CHECK-LABEL: @test11(
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; CHECK-NEXT: icmp
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; CHECK-NEXT: br i1 %tmp455, label %BB4, label %BB2
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%tmp455 = icmp eq i32 %A, 42
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@@ -357,7 +357,7 @@ BB4:
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;; Correlated value through boolean expression. GCC PR18046.
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define void @test12(i32 %A) {
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; CHECK: @test12
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; CHECK-LABEL: @test12(
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entry:
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%cond = icmp eq i32 %A, 0
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br i1 %cond, label %bb, label %bb1
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@@ -393,7 +393,7 @@ return:
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;; rdar://7391699
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define i32 @test13(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test13
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; CHECK-LABEL: @test13(
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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@@ -421,7 +421,7 @@ F2:
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; CHECK-NEXT: br i1 %N, label %T2, label %F2
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}
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; CHECK: @test14
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; CHECK-LABEL: @test14(
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define i32 @test14(i32 %in) {
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entry:
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%A = icmp eq i32 %in, 0
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@@ -453,7 +453,7 @@ right_ret:
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}
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; PR5652
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; CHECK: @test15
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; CHECK-LABEL: @test15(
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define i32 @test15(i32 %len) {
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entry:
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; CHECK: icmp ult i32 %len, 13
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@@ -67,7 +67,7 @@ L2: ; preds = %indirectgoto
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; Don't merge address-taken blocks.
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@.str = private unnamed_addr constant [4 x i8] c"%p\0A\00"
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; CHECK: @test3
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; CHECK-LABEL: @test3(
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; CHECK: __here:
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; CHECK: blockaddress(@test3, %__here)
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; CHECK: __here1:
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@@ -10,7 +10,7 @@ declare void @quux()
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; Mostly theoretical since instruction combining simplifies all selects of
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; booleans where at least one operand is true/false/undef.
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; CHECK: @test_br
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; CHECK-LABEL: @test_br(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 %cond, label %L1,
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define void @test_br(i1 %cond, i1 %value) nounwind {
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@@ -34,7 +34,7 @@ L3:
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; Jump threading of switch with select as condition.
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; CHECK: @test_switch
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; CHECK-LABEL: @test_switch(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 %cond, label %L1,
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define void @test_switch(i1 %cond, i8 %value) nounwind {
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@@ -69,7 +69,7 @@ L4:
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; Jump threading of indirectbr with select as address.
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; CHECK: @test_indirectbr
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; CHECK-LABEL: @test_indirectbr(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 %cond, label %L1, label %L3
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define void @test_indirectbr(i1 %cond, i8* %address) nounwind {
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@@ -93,7 +93,7 @@ L3:
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; A more complicated case: the condition is a select based on a comparison.
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; CHECK: @test_switch_cmp
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; CHECK-LABEL: @test_switch_cmp(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 %cond, label %L0, label %[[THREADED:[A-Za-z.0-9]+]]
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; CHECK: [[THREADED]]:
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@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin7"
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; Test that we can thread through the block with the partially redundant load (%2).
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; rdar://6402033
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define i32 @test1(i32* %P) nounwind {
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; CHECK: @test1
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; CHECK-LABEL: @test1(
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entry:
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%0 = tail call i32 (...)* @f1() nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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@@ -45,7 +45,7 @@ declare i32 @f2(...)
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; rdar://11039258
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define i32 @test2(i32* %P) nounwind {
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; CHECK: @test2
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; CHECK-LABEL: @test2(
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entry:
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%0 = tail call i32 (...)* @f1() nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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