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* Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -455,7 +455,10 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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default: break;
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default:
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if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
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return TLI.isMaskedValueZeroForTargetNode(Op, Mask);
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break;
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}
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return false;
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}
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@ -125,3 +125,8 @@ void TargetLowering::computeRegisterProperties() {
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const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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return NULL;
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}
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bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
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uint64_t Mask) const {
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return false;
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}
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@ -172,6 +172,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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break;
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case ISD::GlobalAddress:
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case ISD::TargetGlobalAddress:
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if (AM.GV == 0) {
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AM.GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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return false;
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@ -122,6 +122,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
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}
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// We don't have line number support yet.
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@ -1051,6 +1052,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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case ISD::GlobalAddress:
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
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// For Darwin, external and weak symbols are indirect, so we want to load
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// the value at address GV, not the value of GV itself. This means that
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// the GlobalAddress must be in the base or index register of the address,
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@ -1058,10 +1060,10 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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if (getTargetMachine().
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getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
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(GV->hasWeakLinkage() || GV->isExternal()))
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return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Op,
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DAG.getSrcValue(NULL));
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return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
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GVOp, DAG.getSrcValue(NULL));
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else
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return Op;
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return GVOp;
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break;
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}
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}
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@ -1086,3 +1088,18 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
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}
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}
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bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
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uint64_t Mask) const {
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unsigned Opc = Op.getOpcode();
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switch (Opc) {
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default:
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assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
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break;
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case X86ISD::SETCC: return (Mask & 1) == 0;
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}
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return false;
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}
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@ -155,6 +155,12 @@ namespace llvm {
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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/// be zero. Op is expected to be a target specific node. Used by DAG
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/// combiner.
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virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
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uint64_t Mask) const;
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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private:
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@ -98,8 +98,8 @@ def brtarget : Operand<OtherVT>;
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// Define X86 specific addressing mode.
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def addr : ComplexPattern<i32, 4, "SelectAddr", []>;
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def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr",
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[add,
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frameindex, constpool, globaladdr, externalsym]>;
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[add, frameindex, constpool,
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globaladdr, tglobaladdr, externalsym]>;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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