From 3a0fccf6a0a1702506b2bf6da1e588b2aadec32c Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Thu, 30 Apr 2015 22:27:20 +0000
Subject: [PATCH] [AArch64] Fix bad register class constraint in fast-isel for
 TST instruction.

rdar://problem/20748715


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236273 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64FastISel.cpp  |  5 ++++-
 test/CodeGen/AArch64/arm64-fast-isel.ll | 10 ++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp
index c3f6859f510..837a31f303f 100644
--- a/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/lib/Target/AArch64/AArch64FastISel.cpp
@@ -2679,8 +2679,11 @@ bool AArch64FastISel::selectSelect(const Instruction *I) {
       return false;
     bool CondIsKill = hasTrivialKill(Cond);
 
+    const MCInstrDesc &II = TII.get(AArch64::ANDSWri);
+    CondReg = constrainOperandRegClass(II, CondReg, 1);
+
     // Emit a TST instruction (ANDS wzr, reg, #imm).
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDSWri),
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
             AArch64::WZR)
         .addReg(CondReg, getKillRegState(CondIsKill))
         .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
diff --git a/test/CodeGen/AArch64/arm64-fast-isel.ll b/test/CodeGen/AArch64/arm64-fast-isel.ll
index a4d08f9016a..a1d51a54cd4 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel.ll
@@ -91,3 +91,13 @@ define void @t6() nounwind {
 }
 
 declare void @llvm.trap() nounwind
+
+define void @ands(i32* %addr) {
+; CHECK-LABEL: ands:
+; CHECK: tst [[COND:w[0-9]+]], #0x1
+; CHECK-NEXT: csel [[COND]],
+entry:
+  %cond91 = select i1 undef, i32 1, i32 2
+  store i32 %cond91, i32* %addr, align 4
+  ret void
+}