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https://github.com/c64scene-ar/llvm-6502.git
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Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field. For those, use [r + imm12] where the immediate is zero. Note the generated assembly code does not look any different after the patch. But the bug would have broken the JIT (if there is Thumb2 support) and it can break later passes which expect the address mode to be well-formed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78658 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
1cf5783dd7
commit
3a21425dbe
@ -607,18 +607,29 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
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SDValue &Base, SDValue &OffImm) {
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// Match simple R + imm12 operands.
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// Match frame index...
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if ((N.getOpcode() != ISD::ADD) && (N.getOpcode() != ISD::SUB)) {
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// Base only.
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if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
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if (N.getOpcode() == ISD::FrameIndex) {
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// Match frame index...
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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OffImm = CurDAG->getTargetConstant(0, EVT::i32);
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return true;
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}
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return false;
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} else if (N.getOpcode() == ARMISD::Wrapper) {
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::TargetConstantPool)
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return false; // We want to select t2LDRpci instead.
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} else
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Base = N;
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OffImm = CurDAG->getTargetConstant(0, EVT::i32);
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return true;
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}
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
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// Let t2LDRi8 handle (R - imm8).
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return false;
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int RHSC = (int)RHS->getZExtValue();
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if (N.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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@ -634,20 +645,23 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
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}
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}
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return false;
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// Base only.
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Base = N;
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OffImm = CurDAG->getTargetConstant(0, EVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
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SDValue &Base, SDValue &OffImm) {
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// Match simple R - imm8 operands.
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if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
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if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getSExtValue();
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if (N.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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if ((RHSC >= -255) && (RHSC <= 0)) { // 8 bits (always negative)
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Base = N.getOperand(0);
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if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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@ -709,40 +723,19 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
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bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
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SDValue &Base,
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SDValue &OffReg, SDValue &ShImm) {
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// Base only.
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if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
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Base = N;
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if (N.getOpcode() == ISD::FrameIndex) {
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return false; // we want to select t2LDRri12 instead
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} else if (N.getOpcode() == ARMISD::Wrapper) {
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::TargetConstantPool)
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return false; // We want to select t2LDRpci instead.
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}
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OffReg = CurDAG->getRegister(0, EVT::i32);
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ShImm = CurDAG->getTargetConstant(0, EVT::i32);
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return true;
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}
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// (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
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if (N.getOpcode() != ISD::ADD)
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return false;
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// Leave (R +/- imm) for other address modes... unless they can't
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// handle them
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if (dyn_cast<ConstantSDNode>(N.getOperand(1)) != NULL) {
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SDValue OffImm;
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if (SelectT2AddrModeImm12(Op, N, Base, OffImm) ||
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SelectT2AddrModeImm8 (Op, N, Base, OffImm))
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// Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
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return false;
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else if (RHSC < 0 && RHSC >= -255) // 8 bits
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return false;
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}
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// Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
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if (N.getOpcode() == ISD::SUB) {
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Base = N;
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OffReg = CurDAG->getRegister(0, EVT::i32);
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ShImm = CurDAG->getTargetConstant(0, EVT::i32);
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return true;
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}
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assert(N.getOpcode() == ISD::ADD);
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// Look for (R + R) or (R + (R << [1,2,3])).
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unsigned ShAmt = 0;
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Base = N.getOperand(0);
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@ -849,14 +849,13 @@ void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
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O << "[" << TRI->getAsmName(MO1.getReg());
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if (MO2.getReg()) {
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O << ", +" << TRI->getAsmName(MO2.getReg());
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assert(MO2.getReg() && "Invalid so_reg load / store address!");
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O << ", +" << TRI->getAsmName(MO2.getReg());
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unsigned ShAmt = MO3.getImm();
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if (ShAmt) {
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assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
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O << ", lsl #" << ShAmt;
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}
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unsigned ShAmt = MO3.getImm();
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if (ShAmt) {
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assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
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O << ", lsl #" << ShAmt;
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}
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O << "]";
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}
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@ -24,6 +24,7 @@ using namespace llvm;
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STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
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STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
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static cl::opt<int> ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden);
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@ -83,7 +84,24 @@ namespace {
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{ ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 }
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{ ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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// FIXME: Clean this up after splitting each Thumb load / store opcode
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// into multiple ones.
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{ ARM::t2LDRi12,ARM::tLDR, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRBi12,ARM::tLDRB, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRHi12,ARM::tLDRH, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRSBs,ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRi12,ARM::tSTR, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRBi12,ARM::tSTRB, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRHi12,ARM::tSTRH, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 }
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};
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class VISIBILITY_HIDDEN Thumb2SizeReduce : public MachineFunctionPass {
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@ -103,6 +121,12 @@ namespace {
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/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
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DenseMap<unsigned, unsigned> ReduceOpcodeMap;
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bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry);
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bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry, bool LiveCPSR);
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/// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
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/// instruction.
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bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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@ -161,6 +185,114 @@ static bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry) {
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unsigned Scale = 1;
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bool HasImmOffset = false;
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bool HasShift = false;
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switch (Entry.WideOpc) {
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default:
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llvm_unreachable("Unexpected Thumb2 load / store opcode!");
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case ARM::t2LDRi12:
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case ARM::t2STRi12:
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Scale = 4;
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HasImmOffset = true;
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break;
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case ARM::t2LDRBi12:
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case ARM::t2STRBi12:
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HasImmOffset = true;
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break;
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case ARM::t2LDRHi12:
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case ARM::t2STRHi12:
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Scale = 2;
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HasImmOffset = true;
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break;
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case ARM::t2LDRs:
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case ARM::t2LDRBs:
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case ARM::t2LDRHs:
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case ARM::t2LDRSBs:
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case ARM::t2LDRSHs:
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case ARM::t2STRs:
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case ARM::t2STRBs:
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case ARM::t2STRHs:
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HasShift = true;
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break;
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}
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unsigned OffsetReg = 0;
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bool OffsetKill = false;
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if (HasShift) {
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OffsetReg = MI->getOperand(2).getReg();
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OffsetKill = MI->getOperand(2).isKill();
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if (MI->getOperand(3).getImm())
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// Thumb1 addressing mode doesn't support shift.
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return false;
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}
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unsigned OffsetImm = 0;
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if (HasImmOffset) {
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OffsetImm = MI->getOperand(2).getImm();
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unsigned MaxOffset = ((1 << Entry.Imm1Limit) - 1) * Scale;
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if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
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// Make sure the immediate field fits.
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return false;
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}
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// Add the 16-bit load / store instruction.
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// FIXME: Thumb1 addressing mode encode both immediate and register offset.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Entry.NarrowOpc1))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1));
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if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) {
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// tLDRSB and tLDRSH do not have an immediate offset field. On the other
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// hand, it must have an offset register.
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assert(OffsetReg && "Invalid so_reg load / store address!");
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// FIXME: Remove this special case.
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MIB.addImm(OffsetImm/Scale);
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}
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MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
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// Transfer the rest of operands.
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unsigned OpNum = HasShift ? 4 : 3;
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for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
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MIB.addOperand(MI->getOperand(OpNum));
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DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
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MBB.erase(MI);
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++NumLdSts;
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return true;
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}
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static bool VerifyLowRegs(MachineInstr *MI, const TargetInstrDesc &TID) {
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for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0 || Reg == ARM::CPSR)
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continue;
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if (!isARMLowRegister(Reg))
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return false;
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}
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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const TargetInstrDesc &TID = MI->getDesc();
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if (Entry.LowRegs1 && !VerifyLowRegs(MI, TID))
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return false;
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if (TID.mayLoad() || TID.mayStore())
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return ReduceLoadStore(MBB, MI, Entry);
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return false;
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}
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bool
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Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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@ -353,8 +485,14 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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if (OPI != ReduceOpcodeMap.end()) {
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const ReduceEntry &Entry = ReduceTable[OPI->second];
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// Ignore "special" cases for now.
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if (Entry.Special)
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if (Entry.Special) {
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if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) {
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Modified = true;
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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}
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goto ProcessNext;
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}
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// Try to transform to a 16-bit two-address instruction.
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if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
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