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R600: Emit ELF formatted code rather than raw ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,7 +44,6 @@ public:
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AMDGPUAsmBackend(const Target &T)
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AMDGPUAsmBackend(const Target &T)
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: MCAsmBackend() {}
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: MCAsmBackend() {}
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virtual AMDGPUMCObjectWriter *createObjectWriter(raw_ostream &OS) const;
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virtual unsigned getNumFixupKinds() const { return 0; };
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virtual unsigned getNumFixupKinds() const { return 0; };
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virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const;
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uint64_t Value) const;
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@ -71,16 +70,6 @@ void AMDGPUMCObjectWriter::WriteObject(MCAssembler &Asm,
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}
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}
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}
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}
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MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, StringRef TT,
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StringRef CPU) {
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return new AMDGPUAsmBackend(T);
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}
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AMDGPUMCObjectWriter * AMDGPUAsmBackend::createObjectWriter(
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raw_ostream &OS) const {
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return new AMDGPUMCObjectWriter(OS);
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}
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void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value) const {
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unsigned DataSize, uint64_t Value) const {
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@ -88,3 +77,21 @@ void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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assert(Fixup.getKind() == FK_PCRel_4);
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assert(Fixup.getKind() == FK_PCRel_4);
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*Dst = (Value - 4) / 4;
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*Dst = (Value - 4) / 4;
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}
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}
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//===----------------------------------------------------------------------===//
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// ELFAMDGPUAsmBackend class
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//===----------------------------------------------------------------------===//
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class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
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public:
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ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createAMDGPUELFObjectWriter(OS);
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}
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};
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MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, StringRef TT,
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StringRef CPU) {
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return new ELFAMDGPUAsmBackend(T);
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}
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39
lib/Target/R600/MCTargetDesc/AMDGPUELFObjectWriter.cpp
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39
lib/Target/R600/MCTargetDesc/AMDGPUELFObjectWriter.cpp
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@ -0,0 +1,39 @@
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//===-- AMDGPUELFObjectWriter.cpp - AMDGPU ELF Writer ----------------------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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using namespace llvm;
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namespace {
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class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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AMDGPUELFObjectWriter();
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protected:
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virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
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bool IsPCRel, bool IsRelocWithSymbol,
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int64_t Addend) const {
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llvm_unreachable("Not implemented");
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}
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};
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} // End anonymous namespace
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AMDGPUELFObjectWriter::AMDGPUELFObjectWriter()
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: MCELFObjectTargetWriter(false, 0, 0, false) { }
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MCObjectWriter *llvm::createAMDGPUELFObjectWriter(raw_ostream &OS) {
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MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter();
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return createELFObjectWriter(MOTW, OS, true);
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}
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@ -88,7 +88,7 @@ static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCCodeEmitter *_Emitter,
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MCCodeEmitter *_Emitter,
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bool RelaxAll,
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bool RelaxAll,
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bool NoExecStack) {
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bool NoExecStack) {
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return createPureStreamer(Ctx, MAB, _OS, _Emitter);
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return createELFStreamer(Ctx, MAB, _OS, _Emitter, false, false);
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}
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}
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extern "C" void LLVMInitializeR600TargetMC() {
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extern "C" void LLVMInitializeR600TargetMC() {
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@ -23,9 +23,11 @@ class MCAsmBackend;
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class MCCodeEmitter;
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class MCCodeEmitter;
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class MCContext;
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class MCContext;
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class MCInstrInfo;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCSubtargetInfo;
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class Target;
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class Target;
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class raw_ostream;
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extern Target TheAMDGPUTarget;
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extern Target TheAMDGPUTarget;
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@ -41,6 +43,8 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
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MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT,
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MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT,
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StringRef CPU);
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StringRef CPU);
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MCObjectWriter *createAMDGPUELFObjectWriter(raw_ostream &OS);
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} // End llvm namespace
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} // End llvm namespace
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_ENUM
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@ -1,6 +1,7 @@
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add_llvm_library(LLVMR600Desc
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add_llvm_library(LLVMR600Desc
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AMDGPUAsmBackend.cpp
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AMDGPUAsmBackend.cpp
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AMDGPUELFObjectWriter.cpp
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AMDGPUMCTargetDesc.cpp
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AMDGPUMCTargetDesc.cpp
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AMDGPUMCAsmInfo.cpp
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AMDGPUMCAsmInfo.cpp
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R600MCCodeEmitter.cpp
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R600MCCodeEmitter.cpp
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11
test/CodeGen/R600/elf.ll
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11
test/CodeGen/R600/elf.ll
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@ -0,0 +1,11 @@
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; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck %s
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; CHECK: Format: ELF32
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define void @test(i32 %p) {
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%i = add i32 %p, 2
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%r = bitcast i32 %i to float
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
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ret void
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}
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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