mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 00:32:55 +00:00
AVX-512: Added more intrinsics for convert and min/max.
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
5c1c0bd714
commit
3a880de6e6
@ -2747,7 +2747,13 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2pd_512 : GCCBuiltin<"__builtin_ia32_cvtdq2pd512_mask">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_v8f64_ty,
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llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvtudq2ps_512 : GCCBuiltin<"__builtin_ia32_cvtudq2ps512_mask">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty, llvm_v16f32_ty,
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llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvtudq2pd_512 : GCCBuiltin<"__builtin_ia32_cvtudq2pd512_mask">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_v8f64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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}
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// Vector load with broadcast
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@ -2800,18 +2806,18 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Arithmetic ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_min_ps_512 : GCCBuiltin<"__builtin_ia32_minps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty,
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llvm_v16f32_ty], [IntrNoMem]>;
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def int_x86_avx512_min_pd_512 : GCCBuiltin<"__builtin_ia32_minpd512">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,
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llvm_v8f64_ty], [IntrNoMem]>;
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def int_x86_avx512_max_ps_512 : GCCBuiltin<"__builtin_ia32_maxps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty,
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llvm_v16f32_ty], [IntrNoMem]>;
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def int_x86_avx512_max_pd_512 : GCCBuiltin<"__builtin_ia32_maxpd512">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,
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llvm_v8f64_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_max_ps_512 : GCCBuiltin<"__builtin_ia32_maxps512_mask">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty,
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llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_max_pd_512 : GCCBuiltin<"__builtin_ia32_maxpd512_mask">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
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llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_min_ps_512 : GCCBuiltin<"__builtin_ia32_minps512_mask">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty,
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llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_min_pd_512 : GCCBuiltin<"__builtin_ia32_minpd512_mask">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
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llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_pmaxu_d : GCCBuiltin<"__builtin_ia32_pmaxud512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
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@ -11462,14 +11462,10 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_sse2_max_pd:
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case Intrinsic::x86_avx_max_ps_256:
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case Intrinsic::x86_avx_max_pd_256:
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case Intrinsic::x86_avx512_max_ps_512:
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case Intrinsic::x86_avx512_max_pd_512:
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case Intrinsic::x86_sse_min_ps:
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case Intrinsic::x86_sse2_min_pd:
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case Intrinsic::x86_avx_min_ps_256:
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case Intrinsic::x86_avx_min_pd_256:
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case Intrinsic::x86_avx512_min_ps_512:
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case Intrinsic::x86_avx512_min_pd_512: {
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case Intrinsic::x86_avx_min_pd_256: {
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unsigned Opcode;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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@ -11477,16 +11473,12 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_sse2_max_pd:
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case Intrinsic::x86_avx_max_ps_256:
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case Intrinsic::x86_avx_max_pd_256:
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case Intrinsic::x86_avx512_max_ps_512:
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case Intrinsic::x86_avx512_max_pd_512:
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Opcode = X86ISD::FMAX;
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break;
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case Intrinsic::x86_sse_min_ps:
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case Intrinsic::x86_sse2_min_pd:
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case Intrinsic::x86_avx_min_ps_256:
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case Intrinsic::x86_avx_min_pd_256:
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case Intrinsic::x86_avx512_min_ps_512:
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case Intrinsic::x86_avx512_min_pd_512:
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Opcode = X86ISD::FMIN;
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break;
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}
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@ -2038,6 +2038,25 @@ defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
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SSE_ALU_ITINS_P.d, 0>,
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EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
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def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
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(v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
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(i16 -1), FROUND_CURRENT)),
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(VMAXPSZrr VR512:$src1, VR512:$src2)>;
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def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
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(v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
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(i8 -1), FROUND_CURRENT)),
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(VMAXPDZrr VR512:$src1, VR512:$src2)>;
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def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
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(v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
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(i16 -1), FROUND_CURRENT)),
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(VMINPSZrr VR512:$src1, VR512:$src2)>;
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def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
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(v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
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(i8 -1), FROUND_CURRENT)),
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(VMINPDZrr VR512:$src1, VR512:$src2)>;
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//===----------------------------------------------------------------------===//
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// AVX-512 VPTESTM instructions
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//===----------------------------------------------------------------------===//
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@ -2731,7 +2750,7 @@ def : Pat<(extloadf32 addr:$src),
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def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
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Requires<[HasAVX512]>;
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multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
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multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
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RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
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X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
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Domain d> {
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@ -2751,7 +2770,7 @@ let neverHasSideEffects = 1 in {
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} // neverHasSideEffects = 1
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}
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multiclass avx512_vcvtt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
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multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
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RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
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X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
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Domain d> {
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@ -2768,8 +2787,7 @@ let neverHasSideEffects = 1 in {
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} // neverHasSideEffects = 1
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}
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defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
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defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
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memopv8f64, f512mem, v8f32, v8f64,
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SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
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EVEX_CD8<64, CD8VF>;
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@ -2784,7 +2802,7 @@ def : Pat<(v8f64 (extloadv8f32 addr:$src)),
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// AVX-512 Vector convert from sign integer to float/double
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//===----------------------------------------------------------------------===//
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defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
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defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
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memopv8i64, i512mem, v16f32, v16i32,
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SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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@ -2793,17 +2811,17 @@ defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
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SSEPackedDouble>, EVEX_V512, XS,
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EVEX_CD8<32, CD8VH>;
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defm VCVTTPS2DQZ : avx512_vcvtt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
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defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
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memopv16f32, f512mem, v16i32, v16f32,
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SSEPackedSingle>, EVEX_V512, XS,
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EVEX_CD8<32, CD8VF>;
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defm VCVTTPD2DQZ : avx512_vcvtt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
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defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
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memopv8f64, f512mem, v8i32, v8f64,
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SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VCVTTPS2UDQZ : avx512_vcvtt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
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defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
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memopv16f32, f512mem, v16i32, v16f32,
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SSEPackedSingle>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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@ -2813,7 +2831,7 @@ def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
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(v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
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(VCVTTPS2UDQZrr VR512:$src)>;
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defm VCVTTPD2UDQZ : avx512_vcvtt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
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defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
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memopv8f64, f512mem, v8i32, v8f64,
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SSEPackedDouble>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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@ -2828,7 +2846,7 @@ defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
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SSEPackedDouble>, EVEX_V512, XS,
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EVEX_CD8<32, CD8VH>;
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defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
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defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
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memopv16i32, f512mem, v16f32, v16i32,
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SSEPackedSingle>, EVEX_V512, XD,
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EVEX_CD8<32, CD8VF>;
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@ -2839,9 +2857,17 @@ def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
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def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
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(v16f32 immAllZerosV), (i16 -1), imm:$rc)),
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(bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
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(VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
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def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
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(bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
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(VCVTDQ2PDZrr VR256X:$src)>;
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def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
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(bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
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(VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
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def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
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(bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
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(VCVTUDQ2PDZrr VR256X:$src)>;
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multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
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RegisterClass DstRC, PatFrag mem_frag,
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@ -17,6 +17,7 @@
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#define DEBUG_TYPE "x86-vzeroupper"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -105,28 +106,20 @@ FunctionPass *llvm::createX86IssueVZeroUpperPass() {
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}
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static bool isYmmReg(unsigned Reg) {
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return (Reg >= X86::YMM0 && Reg <= X86::YMM31);
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}
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static bool isZmmReg(unsigned Reg) {
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return (Reg >= X86::ZMM0 && Reg <= X86::ZMM31);
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return (Reg >= X86::YMM0 && Reg <= X86::YMM15);
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}
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static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) {
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for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(),
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E = MRI.livein_end(); I != E; ++I)
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if (isYmmReg(I->first) || isZmmReg(I->first))
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if (isYmmReg(I->first))
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return true;
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return false;
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}
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static bool clobbersAllYmmRegs(const MachineOperand &MO) {
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for (unsigned reg = X86::YMM0; reg <= X86::YMM31; ++reg) {
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if (!MO.clobbersPhysReg(reg))
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return false;
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}
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for (unsigned reg = X86::ZMM0; reg <= X86::ZMM31; ++reg) {
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for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) {
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if (!MO.clobbersPhysReg(reg))
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return false;
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}
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@ -155,11 +148,7 @@ static bool clobbersAnyYmmReg(MachineInstr *MI) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegMask())
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continue;
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for (unsigned reg = X86::YMM0; reg <= X86::YMM31; ++reg) {
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if (MO.clobbersPhysReg(reg))
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return true;
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}
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for (unsigned reg = X86::ZMM0; reg <= X86::ZMM31; ++reg) {
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for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) {
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if (MO.clobbersPhysReg(reg))
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return true;
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}
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@ -170,6 +159,8 @@ static bool clobbersAnyYmmReg(MachineInstr *MI) {
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/// runOnMachineFunction - Loop over all of the basic blocks, inserting
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/// vzero upper instructions before function calls.
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bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getTarget().getSubtarget<X86Subtarget>().hasAVX512())
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return false;
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TII = MF.getTarget().getInstrInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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bool EverMadeChange = false;
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@ -447,4 +447,70 @@ declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i1> %a0, <8 x i64> %a1,
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%res = call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i8 -1, i32 4)
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ret i8 %res
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}
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declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
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declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
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; cvt intrinsics
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define <16 x float> @test_cvtdq2ps(<16 x i32> %a) {
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;CHECK: vcvtdq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x5b,0xc0]
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%res = call <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
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ret <16 x float>%res
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}
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declare <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32>, <16 x float>, i16, i32)
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define <16 x float> @test_cvtudq2ps(<16 x i32> %a) {
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;CHECK: vcvtudq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7f,0x38,0x7a,0xc0]
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%res = call <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
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ret <16 x float>%res
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}
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declare <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32>, <16 x float>, i16, i32)
|
||||
|
||||
define <8 x double> @test_cvtdq2pd(<8 x i32> %a) {
|
||||
;CHECK: vcvtdq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0xe6,0xc0]
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
|
||||
ret <8 x double>%res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8)
|
||||
|
||||
define <8 x double> @test_cvtudq2pd(<8 x i32> %a) {
|
||||
;CHECK: vcvtudq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0x7a,0xc0]
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
|
||||
ret <8 x double>%res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
|
||||
|
||||
; fp min - max
|
||||
define <16 x float> @test_vmaxps(<16 x float> %a0, <16 x float> %a1) {
|
||||
; CHECK: vmaxps
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1,
|
||||
<16 x float>zeroinitializer, i16 -1, i32 4)
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>,
|
||||
<16 x float>, i16, i32)
|
||||
|
||||
define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
|
||||
; CHECK: vmaxpd
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double> %a0, <8 x double> %a1,
|
||||
<8 x double>zeroinitializer, i8 -1, i32 4)
|
||||
ret <8 x double> %res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double>, <8 x double>,
|
||||
<8 x double>, i8, i32)
|
||||
|
||||
define <16 x float> @test_vminps(<16 x float> %a0, <16 x float> %a1) {
|
||||
; CHECK: vminps
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1,
|
||||
<16 x float>zeroinitializer, i16 -1, i32 4)
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float>, <16 x float>,
|
||||
<16 x float>, i16, i32)
|
||||
|
||||
define <8 x double> @test_vminpd(<8 x double> %a0, <8 x double> %a1) {
|
||||
; CHECK: vminpd
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double> %a0, <8 x double> %a1,
|
||||
<8 x double>zeroinitializer, i8 -1, i32 4)
|
||||
ret <8 x double> %res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double>, <8 x double>,
|
||||
<8 x double>, i8, i32)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user