mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
Don't add implicit operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4817 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
128a7a96f0
commit
3a9a693987
@ -225,12 +225,12 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
|
|||||||
// FIXME: assuming var1, var2 are in memory, if not, spill to
|
// FIXME: assuming var1, var2 are in memory, if not, spill to
|
||||||
// stack first
|
// stack first
|
||||||
case cFloat: // Floats
|
case cFloat: // Floats
|
||||||
BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
|
BuildMI (BB, X86::FLDr4, 1).addReg (reg1);
|
||||||
BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
|
BuildMI (BB, X86::FLDr4, 1).addReg (reg2);
|
||||||
break;
|
break;
|
||||||
case cDouble: // Doubles
|
case cDouble: // Doubles
|
||||||
BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
|
BuildMI (BB, X86::FLDr8, 1).addReg (reg1);
|
||||||
BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
|
BuildMI (BB, X86::FLDr8, 1).addReg (reg2);
|
||||||
break;
|
break;
|
||||||
case cLong:
|
case cLong:
|
||||||
default:
|
default:
|
||||||
@ -522,7 +522,7 @@ void ISel::visitShiftInst (ShiftInst &I) {
|
|||||||
const unsigned *OpTab = // Figure out the operand table to use
|
const unsigned *OpTab = // Figure out the operand table to use
|
||||||
NonConstantOperand[isLeftShift*2+isOperandSigned];
|
NonConstantOperand[isLeftShift*2+isOperandSigned];
|
||||||
|
|
||||||
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
|
BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -225,12 +225,12 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
|
|||||||
// FIXME: assuming var1, var2 are in memory, if not, spill to
|
// FIXME: assuming var1, var2 are in memory, if not, spill to
|
||||||
// stack first
|
// stack first
|
||||||
case cFloat: // Floats
|
case cFloat: // Floats
|
||||||
BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
|
BuildMI (BB, X86::FLDr4, 1).addReg (reg1);
|
||||||
BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
|
BuildMI (BB, X86::FLDr4, 1).addReg (reg2);
|
||||||
break;
|
break;
|
||||||
case cDouble: // Doubles
|
case cDouble: // Doubles
|
||||||
BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
|
BuildMI (BB, X86::FLDr8, 1).addReg (reg1);
|
||||||
BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
|
BuildMI (BB, X86::FLDr8, 1).addReg (reg2);
|
||||||
break;
|
break;
|
||||||
case cLong:
|
case cLong:
|
||||||
default:
|
default:
|
||||||
@ -522,7 +522,7 @@ void ISel::visitShiftInst (ShiftInst &I) {
|
|||||||
const unsigned *OpTab = // Figure out the operand table to use
|
const unsigned *OpTab = // Figure out the operand table to use
|
||||||
NonConstantOperand[isLeftShift*2+isOperandSigned];
|
NonConstantOperand[isLeftShift*2+isOperandSigned];
|
||||||
|
|
||||||
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
|
BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user