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AMDGPU/SI: Fix read2 merging into a super register.
If the read2 produced was supposed to be writing into a super register, it would use the wrong subregister indices. Fix this by inserting copies, so we only ever write to a vreg_64. Run the register coalescer again to clean this up, although this isn't ideal and often does result in an extra move. Also remove the assert that offset1 > offset0. There isn't a real reason to not allow this other than a minor convenience in the compiler, and it doesn't seem worth the effort of avoiding it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
2addf067a2
commit
3aa0d7cb53
@ -271,6 +271,7 @@ void GCNPassConfig::addPreRegAlloc() {
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// also need extra copies to the address operand to be eliminated.
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initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
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insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
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insertPass(&MachineSchedulerID, &RegisterCoalescerID);
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}
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addPass(createSIShrinkInstructionsPass(), false);
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addPass(createSIFixSGPRLiveRangesPass(), false);
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@ -227,9 +227,8 @@ bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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uint8_t Offset0 = Offset0Imm->getImm();
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uint8_t Offset1 = Offset1Imm->getImm();
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assert(Offset1 > Offset0);
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if (Offset1 - Offset0 == 1) {
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if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
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// Each of these offsets is in element sized units, so we need to convert
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// to bytes of the individual reads.
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@ -214,12 +214,11 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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// cases, like vectors of pointers.
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const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
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unsigned DestReg0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst)->getReg();
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unsigned DestReg1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst)->getReg();
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const MachineOperand *Dest0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst);
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const MachineOperand *Dest1 = TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst);
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unsigned Offset0
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= TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
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= TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
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unsigned Offset1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff;
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@ -258,20 +257,43 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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unsigned SubRegIdx0 = (EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
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unsigned SubRegIdx1 = (EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3;
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updateRegDefsUses(DestReg0, DestReg, SubRegIdx0);
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updateRegDefsUses(DestReg1, DestReg, SubRegIdx1);
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LIS->RemoveMachineInstrFromMaps(I);
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// Replacing Paired in the maps with Read2 allows us to avoid updating the
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// live range for the m0 register.
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LIS->ReplaceMachineInstrInMaps(Paired, Read2);
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const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
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// Copy to the old destination registers.
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MachineInstr *Copy0 = BuildMI(*MBB, I, DL, CopyDesc)
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.addOperand(*Dest0) // Copy to same destination including flags and sub reg.
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.addReg(DestReg, 0, SubRegIdx0);
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MachineInstr *Copy1 = BuildMI(*MBB, I, DL, CopyDesc)
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.addOperand(*Dest1)
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.addReg(DestReg, RegState::Kill, SubRegIdx1);
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LIS->InsertMachineInstrInMaps(Read2);
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// repairLiveintervalsInRange() doesn't handle physical register, so we have
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// to update the M0 range manually.
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SlotIndex PairedIndex = LIS->getInstructionIndex(Paired);
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LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI));
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LiveRange::Segment *M0Segment = M0Range.getSegmentContaining(PairedIndex);
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bool UpdateM0Range = M0Segment->end == PairedIndex.getRegSlot();
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// The new write to the original destination register is now the copy. Steal
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// the old SlotIndex.
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LIS->ReplaceMachineInstrInMaps(I, Copy0);
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LIS->ReplaceMachineInstrInMaps(Paired, Copy1);
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I->eraseFromParent();
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Paired->eraseFromParent();
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LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg());
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LIS->shrinkToUses(&AddrRegLI);
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LIS->getInterval(DestReg); // Create new LI
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LIS->createAndComputeVirtRegInterval(DestReg);
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if (UpdateM0Range) {
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SlotIndex Read2Index = LIS->getInstructionIndex(Read2);
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M0Segment->end = Read2Index.getRegSlot();
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}
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DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');
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return Read2.getInstr();
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@ -1,10 +1,10 @@
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; FIXME: We don't get cases where the address was an SGPR because we
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; get a copy to the address register for each one.
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@lds = addrspace(3) global [512 x float] undef, align 4
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@lds.f64 = addrspace(3) global [512 x double] undef, align 8
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@lds.f64 = addrspace(3) global [512 x double] undef, align 8
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; SI-LABEL: @simple_read2_f32
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; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:8
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@ -1,16 +1,17 @@
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; XFAIL: *
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@lds = addrspace(3) global [512 x float] undef, align 4
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; offset0 is larger than offset1
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; SI-LABEL: {{^}}offset_order:
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; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:56
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; SI: ds_read2st64_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:0 offset1:4
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; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3
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; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:1
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; SI: ds_read2st64_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset1:4{{$}}
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; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:3 offset1:2
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; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:12 offset1:14
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; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:44
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define void @offset_order(float addrspace(1)* %out) {
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entry:
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246
test/CodeGen/AMDGPU/ds_read2_superreg.ll
Normal file
246
test/CodeGen/AMDGPU/ds_read2_superreg.ll
Normal file
@ -0,0 +1,246 @@
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI %s
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@lds = addrspace(3) global [512 x float] undef, align 4
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@lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4
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@lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4
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@lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4
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@lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4
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@lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4
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; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:
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; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
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; CI: s_waitcnt lgkmcnt(0)
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; CI: buffer_store_dwordx2 [[RESULT]]
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; CI: s_endpgm
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define void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
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%val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4
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%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
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store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v2f32_superreg:
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; CI: ds_read_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}
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; CI: s_waitcnt lgkmcnt(0)
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; CI: buffer_store_dwordx2 [[RESULT]]
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; CI: s_endpgm
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define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
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%val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
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store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
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ret void
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}
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; FIXME: Shuffling to new superregister
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Y:[0-9]+]]:[[REG_X:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI-DAG: v_mov_b32_e32 v[[COPY_REG_Y:[0-9]+]], v[[REG_Y]]
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; CI-DAG: v_mov_b32_e32 v[[COPY_REG_Z:[0-9]+]], v[[REG_Z]]
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[COPY_REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[COPY_REG_Y]]
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; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD1]], v[[ADD0]]
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; CI: buffer_store_dword v[[ADD2]]
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
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%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
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%elt0 = extractelement <4 x float> %val0, i32 0
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%elt1 = extractelement <4 x float> %val0, i32 1
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%elt2 = extractelement <4 x float> %val0, i32 2
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%elt3 = extractelement <4 x float> %val0, i32 3
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%add0 = fadd float %elt0, %elt2
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%add1 = fadd float %elt1, %elt3
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%add2 = fadd float %add0, %add1
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
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store float %add2, float addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[ADD0]]
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; CI: buffer_store_dword v[[ADD1]]
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; CI: s_endpgm
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define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i
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%val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4
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%elt0 = extractelement <3 x float> %val0, i32 0
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%elt1 = extractelement <3 x float> %val0, i32 1
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%elt2 = extractelement <3 x float> %val0, i32 2
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%add0 = fadd float %elt0, %elt2
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%add1 = fadd float %add0, %elt1
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
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store float %add1, float addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: buffer_store_dwordx4
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
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%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 8
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%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
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store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: buffer_store_dwordx4
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
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%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
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store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v8f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: s_endpgm
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define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <8 x float>], [512 x <8 x float>] addrspace(3)* @lds.v8, i32 0, i32 %x.i
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%val0 = load <8 x float>, <8 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <8 x float>, <8 x float> addrspace(1)* %out, i32 %x.i
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store <8 x float> %val0, <8 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v16f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:15 offset1:14{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:13 offset1:12{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:11 offset1:10{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:9 offset1:8{{$}}
|
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
|
||||
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
|
||||
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
|
||||
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
|
||||
|
||||
; CI: s_waitcnt lgkmcnt(0)
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: buffer_store_dword
|
||||
; CI: s_endpgm
|
||||
define void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
%arrayidx0 = getelementptr inbounds [512 x <16 x float>], [512 x <16 x float>] addrspace(3)* @lds.v16, i32 0, i32 %x.i
|
||||
%val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0
|
||||
%out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i
|
||||
store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; Do scalar loads into the super register we need.
|
||||
; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4:
|
||||
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
|
||||
; CI-NOT: v_mov
|
||||
; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}}
|
||||
; CI: s_endpgm
|
||||
define void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
|
||||
%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
|
||||
|
||||
%val0 = load float, float addrspace(3)* %arrayidx0
|
||||
%val1 = load float, float addrspace(3)* %arrayidx1
|
||||
|
||||
%vec.0 = insertelement <2 x float> undef, float %val0, i32 0
|
||||
%vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1
|
||||
|
||||
%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
|
||||
store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; Do scalar loads into the super register we need.
|
||||
; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4:
|
||||
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
|
||||
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
|
||||
; CI-NOT: v_mov
|
||||
; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}}
|
||||
; CI: s_endpgm
|
||||
define void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
|
||||
%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
|
||||
%arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2
|
||||
%arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3
|
||||
|
||||
%val0 = load float, float addrspace(3)* %arrayidx0
|
||||
%val1 = load float, float addrspace(3)* %arrayidx1
|
||||
%val2 = load float, float addrspace(3)* %arrayidx2
|
||||
%val3 = load float, float addrspace(3)* %arrayidx3
|
||||
|
||||
%vec.0 = insertelement <4 x float> undef, float %val0, i32 0
|
||||
%vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1
|
||||
%vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2
|
||||
%vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3
|
||||
|
||||
%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
|
||||
store <4 x float> %vec.3, <4 x float> addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tgid.x() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tgid.y() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tidig.x() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tidig.y() #1
|
||||
|
||||
; Function Attrs: noduplicate nounwind
|
||||
declare void @llvm.AMDGPU.barrier.local() #2
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
attributes #2 = { noduplicate nounwind }
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s
|
||||
|
||||
@lds = addrspace(3) global [512 x float] undef, align 4
|
||||
@lds.f64 = addrspace(3) global [512 x double] undef, align 8
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
|
||||
|
||||
@lds = addrspace(3) global [512 x float] undef, align 4
|
||||
@lds.f64 = addrspace(3) global [512 x double] undef, align 8
|
||||
@ -25,7 +25,7 @@ define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1
|
||||
; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
@ -405,6 +405,19 @@ define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, f
|
||||
ret void
|
||||
}
|
||||
|
||||
; CI-LABEL: {{^}}simple_write2_v4f32_superreg_align4:
|
||||
; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:3 offset1:2{{$}}
|
||||
; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:1{{$}}
|
||||
; CI: s_endpgm
|
||||
define void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, <4 x float> addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
%in.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in
|
||||
%val0 = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 4
|
||||
%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(3)* %out, i32 %x.i
|
||||
store <4 x float> %val0, <4 x float> addrspace(3)* %out.gep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tgid.x() #1
|
||||
|
||||
|
||||
@ -1,9 +1,7 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
|
||||
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s
|
||||
|
||||
@lds = addrspace(3) global [512 x float] undef, align 4
|
||||
|
||||
|
||||
; SI-LABEL: @simple_write2st64_one_val_f32_0_1
|
||||
; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user