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R600: Reorganize lit tests and document how they should be organized
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8
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21
test/CodeGen/R600/README
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21
test/CodeGen/R600/README
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@ -0,0 +1,21 @@
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+==============================================================================+
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| How to organize the lit tests |
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+==============================================================================+
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- If you write a test for matching a single DAG opcode or intrinsic, it should
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go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)
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- If you write a test that matches several DAG opcodes and checks for a single
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ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
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bfi_int.ll
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- For all other tests, use your best judgement for organizing tests and naming
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the files.
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+==============================================================================+
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| Naming conventions |
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+==============================================================================+
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- Use dash '-' and not underscore '_' to separate words in file names, unless
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the file is named after a DAG opcode or ISA instruction that has an
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underscore '_' in its name.
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@ -1,8 +1,9 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fadd_f32
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test() {
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define void @fadd_f32() {
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%r0 = call float @llvm.R600.load.input(i32 0)
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%r1 = call float @llvm.R600.load.input(i32 1)
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%r2 = fadd float %r0, %r1
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@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fadd_v4f32
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fadd <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,15 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fadd <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,8 +1,9 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fmul_f32
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test() {
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define void @fmul_f32() {
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%r0 = call float @llvm.R600.load.input(i32 0)
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%r1 = call float @llvm.R600.load.input(i32 1)
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%r2 = fmul float %r0, %r1
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@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fmul_v4f32
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fmul <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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14
test/CodeGen/R600/fp_to_sint.ll
Normal file
14
test/CodeGen/R600/fp_to_sint.ll
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@ -0,0 +1,14 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fp_to_sint_v4i32
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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%result = fptosi <4 x float> %value to <4 x i32>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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14
test/CodeGen/R600/fp_to_uint.ll
Normal file
14
test/CodeGen/R600/fp_to_uint.ll
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@ -0,0 +1,14 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fp_to_uint_v4i32
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; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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%result = fptoui <4 x float> %value to <4 x i32>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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@ -1,8 +1,9 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fsub_f32
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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define void @test() {
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define void @fsub_f32() {
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%r0 = call float @llvm.R600.load.input(i32 0)
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%r1 = call float @llvm.R600.load.input(i32 1)
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%r2 = fsub float %r0, %r1
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@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fsub_v4f32
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fsub <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fsub <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,9 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
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define void @test(float addrspace(1)* %out, float addrspace(2)* %in) {
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%1 = load float addrspace(2)* %in
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store float %1, float addrspace(1)* %out
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ret void
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}
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@ -1,10 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%1 = load i8 addrspace(1)* %in
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%2 = zext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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20
test/CodeGen/R600/load.ll
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20
test/CodeGen/R600/load.ll
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; Load an i8 value from the global address space.
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; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%1 = load i8 addrspace(1)* %in
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%2 = zext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; Load a f32 value from the constant address space.
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; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
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define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
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%1 = load float addrspace(2)* %in
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store float %1, float addrspace(1)* %out
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ret void
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}
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14
test/CodeGen/R600/sint_to_fp.ll
Normal file
14
test/CodeGen/R600/sint_to_fp.ll
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @sint_to_fp_v4i32
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; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%value = load <4 x i32> addrspace(1) * %in
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%result = sitofp <4 x i32> %value to <4 x float>
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,11 +1,13 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
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; CHECK: @store_float
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; floating-point store
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; EG-CHECK: @store_f32
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; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
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; SI-CHECK: @store_f32
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; SI-CHECK: BUFFER_STORE_DWORD
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define void @store_float(float addrspace(1)* %out, float %in) {
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define void @store_f32(float addrspace(1)* %out, float %in) {
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store float %in, float addrspace(1)* %out
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ret void
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}
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22
test/CodeGen/R600/store.r600.ll
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22
test/CodeGen/R600/store.r600.ll
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; XXX: Merge this test into store.ll once it is supported on SI
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; v4i32 store
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; EG-CHECK: @store_v4i32
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; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
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define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%1 = load <4 x i32> addrspace(1) * %in
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store <4 x i32> %1, <4 x i32> addrspace(1)* %out
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ret void
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}
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; v4f32 store
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; EG-CHECK: @store_v4f32
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; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
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define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%1 = load <4 x float> addrspace(1) * %in
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store <4 x float> %1, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,9 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%1 = load <4 x float> addrspace(1) * %in
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store <4 x float> %1, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,9 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
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define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%1 = load <4 x i32> addrspace(1) * %in
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store <4 x i32> %1, <4 x i32> addrspace(1)* %out
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ret void
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}
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14
test/CodeGen/R600/uint_to_fp.ll
Normal file
14
test/CodeGen/R600/uint_to_fp.ll
Normal file
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @uint_to_fp_v4i32
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; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%value = load <4 x i32> addrspace(1) * %in
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%result = uitofp <4 x i32> %value to <4 x float>
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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@ -1,53 +0,0 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fp_to_sint
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fp_to_sint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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%result = fptosi <4 x float> %value to <4 x i32>
|
||||
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @fp_to_uint
|
||||
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
define void @fp_to_uint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
%value = load <4 x float> addrspace(1) * %in
|
||||
%result = fptoui <4 x float> %value to <4 x i32>
|
||||
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @sint_to_fp
|
||||
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
define void @sint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
%value = load <4 x i32> addrspace(1) * %in
|
||||
%result = sitofp <4 x i32> %value to <4 x float>
|
||||
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @uint_to_fp
|
||||
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
define void @uint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
%value = load <4 x i32> addrspace(1) * %in
|
||||
%result = uitofp <4 x i32> %value to <4 x float>
|
||||
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
Loading…
Reference in New Issue
Block a user