Correct macro names per naming standard in Makefile.rules

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17360 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reid Spencer 2004-10-30 09:25:27 +00:00
parent cc2d1e25f3
commit 3abd4974ba

View File

@ -36,32 +36,32 @@ STKRC_EXEC = $(BUILD_OBJ_ROOT)/tools/$(CONFIGURATION)/stkrc
all :: test_each
test_each: $(TESTS)
@$(ECHO) "Running Tests..."
$(VERB) LD_LIBRARY_PATH=$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) $(BUILD_SRC_DIR)/runtests $(BUILD_OBJ_DIR) $(TESTS)
$(Echo) "Running Tests..."
$(Verb) LD_LIBRARY_PATH=$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) $(BUILD_SRC_DIR)/runtests $(BUILD_OBJ_DIR) $(TESTS)
%.bc : %.st Makefile
@$(ECHO) "Compiling And Optimizing $< to $*.bc"
$(VERB)$(STKRC_EXEC) -f -O4 -s 2048 -o $*.bc $(BUILD_SRC_DIR)/$*.st
$(Echo) "Compiling And Optimizing $< to $*.bc"
$(Verb)$(STKRC_EXEC) -f -O4 -s 2048 -o $*.bc $(BUILD_SRC_DIR)/$*.st
%.s : %.bc testing.bc
@$(ECHO) "Assembling $< to $*.s"
$(VERB)$(LLINK) $*.bc testing.bc -o $*.bcl
$(VERB)$(LLC) -f -o $*.s $*.bcl
$(Echo) "Assembling $< to $*.s"
$(Verb)$(LLINK) $*.bc testing.bc -o $*.bcl
$(Verb)$(LLC) -f -o $*.s $*.bcl
% : %.s
@$(ECHO) "Linking $*"
$(VERB)$(CC) -ggdb -L$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) -lstkr_runtime -o $* $*.s
$(Echo) "Linking $*"
$(Verb)$(CC) -ggdb -L$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) -lstkr_runtime -o $* $*.s
%.ll : %.bc
@$(ECHO) "Disassembling $< to $*.ll"
$(VERB)$(LDIS) -dis -o $*.ll $<
$(Echo) "Disassembling $< to $*.ll"
$(Verb)$(LDIS) -dis -o $*.ll $<
TESTS_LL = $(TESTS:%=%.ll)
TESTS_BC = $(TESTS:%=%.bc)
TESTS_S = $(TESTS:%=%.s)
clean ::
$(VERB)rm -f gmon.out $(TESTS_LL) $(TESTS_BC) $(TESTS_S) $(TESTS) testing.bc testing.s testing.ll
$(Verb)rm -f gmon.out $(TESTS_LL) $(TESTS_BC) $(TESTS_S) $(TESTS) testing.bc testing.s testing.ll
.SUFFIXES: .st .s .ll .bc
.PRECIOUS: %.s %.ll %.bc %.st