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Correct macro names per naming standard in Makefile.rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17360 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,32 +36,32 @@ STKRC_EXEC = $(BUILD_OBJ_ROOT)/tools/$(CONFIGURATION)/stkrc
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all :: test_each
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test_each: $(TESTS)
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@$(ECHO) "Running Tests..."
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$(VERB) LD_LIBRARY_PATH=$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) $(BUILD_SRC_DIR)/runtests $(BUILD_OBJ_DIR) $(TESTS)
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$(Echo) "Running Tests..."
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$(Verb) LD_LIBRARY_PATH=$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) $(BUILD_SRC_DIR)/runtests $(BUILD_OBJ_DIR) $(TESTS)
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%.bc : %.st Makefile
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@$(ECHO) "Compiling And Optimizing $< to $*.bc"
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$(VERB)$(STKRC_EXEC) -f -O4 -s 2048 -o $*.bc $(BUILD_SRC_DIR)/$*.st
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$(Echo) "Compiling And Optimizing $< to $*.bc"
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$(Verb)$(STKRC_EXEC) -f -O4 -s 2048 -o $*.bc $(BUILD_SRC_DIR)/$*.st
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%.s : %.bc testing.bc
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@$(ECHO) "Assembling $< to $*.s"
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$(VERB)$(LLINK) $*.bc testing.bc -o $*.bcl
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$(VERB)$(LLC) -f -o $*.s $*.bcl
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$(Echo) "Assembling $< to $*.s"
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$(Verb)$(LLINK) $*.bc testing.bc -o $*.bcl
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$(Verb)$(LLC) -f -o $*.s $*.bcl
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% : %.s
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@$(ECHO) "Linking $*"
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$(VERB)$(CC) -ggdb -L$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) -lstkr_runtime -o $* $*.s
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$(Echo) "Linking $*"
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$(Verb)$(CC) -ggdb -L$(BUILD_OBJ_ROOT)/lib/$(CONFIGURATION) -lstkr_runtime -o $* $*.s
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%.ll : %.bc
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@$(ECHO) "Disassembling $< to $*.ll"
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$(VERB)$(LDIS) -dis -o $*.ll $<
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$(Echo) "Disassembling $< to $*.ll"
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$(Verb)$(LDIS) -dis -o $*.ll $<
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TESTS_LL = $(TESTS:%=%.ll)
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TESTS_BC = $(TESTS:%=%.bc)
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TESTS_S = $(TESTS:%=%.s)
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clean ::
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$(VERB)rm -f gmon.out $(TESTS_LL) $(TESTS_BC) $(TESTS_S) $(TESTS) testing.bc testing.s testing.ll
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$(Verb)rm -f gmon.out $(TESTS_LL) $(TESTS_BC) $(TESTS_S) $(TESTS) testing.bc testing.s testing.ll
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.SUFFIXES: .st .s .ll .bc
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.PRECIOUS: %.s %.ll %.bc %.st
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