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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2011-09-20 03:06:13 +00:00
parent a54b3ac96e
commit 3af7a67629
3 changed files with 43 additions and 43 deletions
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22
lib/Target/ARM/ARMISelLowering.cpp
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@ -7928,7 +7928,7 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
return RCPair(0U, ARM::GPRRegisterClass);
case 'h': // High regs or no regs.
if (Subtarget->isThumb())
return RCPair(0U, ARM::hGPRRegisterClass);
return RCPair(0U, ARM::hGPRRegisterClass);
break;
case 'r':
return RCPair(0U, ARM::GPRRegisterClass);
@ -7942,15 +7942,15 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
break;
case 'x':
if (VT == MVT::f32)
return RCPair(0U, ARM::SPR_8RegisterClass);
return RCPair(0U, ARM::SPR_8RegisterClass);
if (VT.getSizeInBits() == 64)
return RCPair(0U, ARM::DPR_8RegisterClass);
return RCPair(0U, ARM::DPR_8RegisterClass);
if (VT.getSizeInBits() == 128)
return RCPair(0U, ARM::QPR_8RegisterClass);
return RCPair(0U, ARM::QPR_8RegisterClass);
break;
case 't':
if (VT == MVT::f32)
return RCPair(0U, ARM::SPRRegisterClass);
return RCPair(0U, ARM::SPRRegisterClass);
break;
}
}
@ -7990,12 +7990,12 @@ void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
switch (ConstraintLetter) {
case 'j':
// Constant suitable for movw, must be between 0 and
// 65535.
if (Subtarget->hasV6T2Ops())
if (CVal >= 0 && CVal <= 65535)
break;
return;
// Constant suitable for movw, must be between 0 and
// 65535.
if (Subtarget->hasV6T2Ops())
if (CVal >= 0 && CVal <= 65535)
break;
return;
case 'I':
if (Subtarget->isThumb1Only()) {
// This must be a constant between 0 and 255, for ADD