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Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171356 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
3cca7df7c7
commit
3af9323228
@ -2936,6 +2936,26 @@ def SSE_RCPS : OpndItins<
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/// sse1_fp_unop_s - SSE1 unops in scalar form.
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multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
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let Predicates = [HasAVX], hasSideEffects = 0 in {
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def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
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(ins FR32:$src1, FR32:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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let mayLoad = 1 in {
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def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
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(ins FR32:$src1,f32mem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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}
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}
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode FR32:$src))]>;
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@ -2955,19 +2975,50 @@ multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
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}
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/// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
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multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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/// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
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multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins> {
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let Predicates = [HasAVX], hasSideEffects = 0 in {
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def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
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(ins FR32:$src1, FR32:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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let mayLoad = 1 in {
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def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
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(ins FR32:$src1,f32mem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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}
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}
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode FR32:$src))]>;
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// For scalar unary operations, fold a load into the operation
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// only in OptForSize mode. It eliminates an instruction, but it also
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// eliminates a whole-register clobber (the load), so it introduces a
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// partial register update condition.
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def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
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Requires<[UseSSE1, OptForSize]>;
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let Constraints = "$src1 = $dst" in {
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def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[], itins.rr>;
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let mayLoad = 1, hasSideEffects = 0 in
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[], itins.rm>;
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}
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}
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@ -3046,6 +3097,26 @@ let Predicates = [HasAVX] in {
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/// sse2_fp_unop_s - SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
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let Predicates = [HasAVX], hasSideEffects = 0 in {
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def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
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(ins FR64:$src1, FR64:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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let mayLoad = 1 in {
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def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
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(ins FR64:$src1,f64mem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2),
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!strconcat(!strconcat("v", OpcodeStr),
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_LIG;
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}
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}
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def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
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@ -3062,24 +3133,7 @@ multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
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}
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/// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
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let hasSideEffects = 0 in
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multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
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def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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let mayLoad = 1 in {
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def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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}
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}
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/// sse2_fp_unop_p_new - SSE2 unops in vector forms.
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/// sse2_fp_unop_p - SSE2 unops in vector forms.
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multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
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SDNode OpNode, OpndItins itins> {
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let Predicates = [HasAVX] in {
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@ -3113,26 +3167,25 @@ let Predicates = [HasAVX] in {
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[(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
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}
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defm SQRT : sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
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// Square root.
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defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
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SSE_SQRTS>,
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sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
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sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
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SSE_SQRTS>,
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sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;
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defm RSQRT : sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
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sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,
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sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
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int_x86_avx_rsqrt_ps_256, SSE_SQRTP>;
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defm RCP : sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
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defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
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sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
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sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
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int_x86_avx_rcp_ps_256, SSE_RCPP>;
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let Predicates = [HasAVX] in {
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// Square root.
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defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
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sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
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defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
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}
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def : Pat<(f32 (fsqrt FR32:$src)),
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(VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
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def : Pat<(f32 (fsqrt (load addr:$src))),
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@ -3186,49 +3239,11 @@ let Predicates = [HasAVX] in {
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(VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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}
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// Square root.
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defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
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SSE_SQRTS>,
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sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
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SSE_SQRTS>;
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/// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
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multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins> {
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode FR32:$src))]>;
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// For scalar unary operations, fold a load into the operation
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// only in OptForSize mode. It eliminates an instruction, but it also
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// eliminates a whole-register clobber (the load), so it introduces a
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// partial register update condition.
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def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
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Requires<[UseSSE1, OptForSize]>;
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let Constraints = "$src1 = $dst" in {
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def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[], itins.rr>;
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let mayLoad = 1, hasSideEffects = 0 in
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[], itins.rm>;
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}
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}
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>;
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let Predicates = [UseSSE1] in {
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def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
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(RSQRTSSr_Int VR128:$src, VR128:$src)>;
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}
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defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>;
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let Predicates = [UseSSE1] in {
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def : Pat<(int_x86_sse_rcp_ss VR128:$src),
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(RCPSSr_Int VR128:$src, VR128:$src)>;
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}
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