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Make sub- and super- register classes const.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29200 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2006-07-19 05:58:18 +00:00
parent 10d9d9f27c
commit 3b0c0148ed
2 changed files with 8 additions and 7 deletions
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6
include/llvm/Target/MRegisterInfo.h
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@@ -47,7 +47,7 @@ public:
typedef const unsigned* const_iterator;
typedef const MVT::ValueType* vt_iterator;
typedef const TargetRegisterClass** sc_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
bool isSubClass;
const vt_iterator VTs;
@@ -57,8 +57,8 @@ private:
const iterator RegsBegin, RegsEnd;
public:
TargetRegisterClass(const MVT::ValueType *vts,
const TargetRegisterClass **subcs,
const TargetRegisterClass **supcs,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: VTs(vts), SubClasses(subcs), SuperClasses(supcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}