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https://github.com/c64scene-ar/llvm-6502.git
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Recommit r150328. Previous test failures should be fixed by r150360.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
3434b4354a
commit
3b17bf9a7c
@ -348,18 +348,6 @@ def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(cast<ShuffleVectorSDNode>(N)));
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}]>;
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// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
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// PSHUFHW imm.
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def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
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}]>;
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// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
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// PSHUFLW imm.
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def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
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}]>;
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// EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
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// to VEXTRACTF128 imm.
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def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
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@ -407,21 +395,6 @@ def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
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return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
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}]>;
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def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_shuf_imm>;
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def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_pshufhw_imm>;
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def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_pshuflw_imm>;
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def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
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(extract_subvector node:$bigvec,
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node:$index), [{
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@ -2270,17 +2270,6 @@ let Predicates = [HasAVX] in {
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def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
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(VSHUFPSrri VR128:$src2, VR128:$src1,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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// Special unary SHUFPSrri case.
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def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
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(VSHUFPSrri VR128:$src1, VR128:$src1,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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// Special unary SHUFPDrri cases.
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def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
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(VSHUFPDrri VR128:$src1, VR128:$src1,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
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(VSHUFPDrri VR128:$src1, VR128:$src1,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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def : Pat<(v2i64 (X86Shufp VR128:$src1,
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(memopv2i64 addr:$src2), (i8 imm:$imm))),
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@ -3848,21 +3837,19 @@ defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
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//===---------------------------------------------------------------------===//
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let ExeDomain = SSEPackedInt in {
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multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
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PatFrag bc_frag> {
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multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
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def ri : Ii8<0x70, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
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(undef))))]>;
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(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))]>;
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def mi : Ii8<0x70, MRMSrcMem,
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(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (vt (pshuf_frag:$src2
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(bc_frag (memopv2i64 addr:$src1)),
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(undef))))]>;
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(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
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(i8 imm:$src2))))]>;
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}
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multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
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@ -3882,44 +3869,19 @@ def Ymi : Ii8<0x70, MRMSrcMem,
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} // ExeDomain = SSEPackedInt
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let Predicates = [HasAVX] in {
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let AddedComplexity = 5 in
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defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
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VEX;
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let AddedComplexity = 5 in
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defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
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// SSE2 with ImmT == Imm8 and XS prefix.
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defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
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VEX;
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// SSE2 with ImmT == Imm8 and XS prefix.
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defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
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// SSE2 with ImmT == Imm8 and XD prefix.
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defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
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VEX;
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// SSE2 with ImmT == Imm8 and XD prefix.
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defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
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let AddedComplexity = 5 in
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def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
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(VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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// Unary v4f32 shuffle with VPSHUF* in order to fold a load.
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def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
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(VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
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(i8 imm:$imm))),
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(VPSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
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(VPSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
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(VPSHUFHWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(VPSHUFHWmi addr:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
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(VPSHUFLWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(VPSHUFLWmi addr:$src, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
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(VPSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>;
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}
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let Predicates = [HasAVX2] in {
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@ -3929,41 +3891,19 @@ let Predicates = [HasAVX2] in {
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}
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let Predicates = [HasSSE2] in {
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let AddedComplexity = 5 in
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defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
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let AddedComplexity = 5 in
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defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
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// SSE2 with ImmT == Imm8 and XS prefix.
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defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
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// SSE2 with ImmT == Imm8 and XS prefix.
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defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
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// SSE2 with ImmT == Imm8 and XD prefix.
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defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
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// SSE2 with ImmT == Imm8 and XD prefix.
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defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
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let AddedComplexity = 5 in
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def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
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(PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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// Unary v4f32 shuffle with PSHUF* in order to fold a load.
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def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
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(PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
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(i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
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(PSHUFHWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(PSHUFHWmi addr:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
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(PSHUFLWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(PSHUFLWmi addr:$src, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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}
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//===---------------------------------------------------------------------===//
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