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Update PPCRegisterInfo's use of virtual registers to be SSA
PPC's use of PEI's virtual-register-based scavenging functionality had redefined the virtual registers (it was non-SSA). Now that PEI supports dealing with instructions with multiple virtual registers, this can be cleanup up to use multiple virtual registers and keep SSA form. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178059 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -578,13 +578,15 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC);
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const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
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unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
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SReg = MF.getRegInfo().createVirtualRegister(RC);
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// Insert a set of rA with the full offset value before the ld, st, or add
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BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
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BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
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.addImm(Offset >> 16);
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BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
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.addReg(SReg, RegState::Kill)
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.addReg(SRegHi, RegState::Kill)
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.addImm(Offset);
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// Convert into indexed form of the instruction:
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