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[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions.

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The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214500 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2014-08-01 12:08:04 +00:00
parent 9bd0d2a6a0
commit 3b3fa38731
2 changed files with 39 additions and 1 deletions
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8
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5754,7 +5754,13 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::LDRH_PRE:
case ARM::LDRH_POST:
case ARM::LDRSH_PRE:
case ARM::LDRSH_POST: {
case ARM::LDRSH_POST:
case ARM::LDRB_PRE_IMM:
case ARM::LDRB_PRE_REG:
case ARM::LDRB_POST_IMM:
case ARM::LDRB_POST_REG:
case ARM::LDRSB_PRE:
case ARM::LDRSB_POST: {
// Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());

32
test/MC/ARM/diagnostics.s
View File

@ -553,6 +553,14 @@ foo2:
ldrsh r0, [r0, r1]!
ldrsh r0, [r0], #2
ldrsh r0, [r0], r1
ldrb r0, [r0, #1]!
ldrb r0, [r0, r1]!
ldrb r0, [r0], #1
ldrb r0, [r0], r1
ldrsb r0, [r0, #1]!
ldrsb r0, [r0, r1]!
ldrsb r0, [r0], #1
ldrsb r0, [r0], r1
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ -589,3 +597,27 @@ foo2:
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0], #1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0], #1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0], r1
@ CHECK-ERRORS: ^