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Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -175,6 +175,11 @@ static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -597,6 +602,40 @@ DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a L6R instruction.
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Inst.clear();
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unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
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switch (Opcode) {
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case 0x00:
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Inst.setOpcode(XCore::LMUL_l6r);
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return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus
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DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3, Op4, Op5;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S != MCDisassembler::Success)
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return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
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S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
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if (S != MCDisassembler::Success)
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return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -222,8 +222,13 @@ class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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let Inst{31-27} = opc{5-1};
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let Inst{20} = opc{0};
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let Inst{15-11} = 0b11111;
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let DecoderMethod = "DecodeL5RInstruction";
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}
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class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -485,17 +485,16 @@ def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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// Five operand long
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def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
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def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"ladd $dst2, $dst1, $src1, $src2, $src3",
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[]>;
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def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
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def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"lsub $dst2, $dst1, $src1, $src2, $src3",
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[]>;
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"lsub $dst2, $dst1, $src1, $src2, $src3", []>;
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def LDIVU_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
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def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
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@ -461,3 +461,14 @@
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# CHECK: lmul r11, r0, r2, r5, r8, r10
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0xf9 0xfa 0x02 0x06
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# l5r instructions
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# CHECK: ladd r10, r2, r5, r1, r7
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0xe5 0xf8 0xfb 0x06
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# CHECK: ldivu r5, r6, r3, r9, r8
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0x54 0xfe 0x0b 0x07
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# CHECK: lsub r1, r8, r7, r11, r5
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0xcf 0xfd 0x85 0x0f
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