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If the register allocator cannot find a register to spill, try the aliases. If

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that still fails (because all the register spill weights are inf), just grab
one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28262 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-05-12 19:07:46 +00:00
parent 0bbac9ffd1
commit 3b6d56cab3
1 changed files with 19 additions and 2 deletions
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21
lib/CodeGen/RegAllocLinearScan.cpp
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@ -551,15 +551,32 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
} }
// If we didn't find a register that is spillable, try aliases? // If we didn't find a register that is spillable, try aliases?
if (!minReg) {
for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
e = RC->allocation_order_end(*mf_); i != e; ++i) {
unsigned reg = *i;
// No need to worry about if the alias register size < regsize of RC.
// We are going to spill all registers that alias it anyway.
for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) {
if (minWeight > SpillWeights[*as]) {
minWeight = SpillWeights[*as];
minReg = *as;
}
}
}
// All registers must have inf weight. Just grab one!
if (!minReg)
minReg = *RC->allocation_order_begin(*mf_);
}
// FIXME: assert(minReg && "Didn't find any reg!");
DEBUG(std::cerr << "\t\tregister with min weight: " DEBUG(std::cerr << "\t\tregister with min weight: "
<< mri_->getName(minReg) << " (" << minWeight << ")\n"); << mri_->getName(minReg) << " (" << minWeight << ")\n");
// if the current has the minimum weight, we need to spill it and // if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart // add any added intervals back to unhandled, and restart
// linearscan. // linearscan.
if (cur->weight <= minWeight) { if (cur->weight != float(HUGE_VAL) && cur->weight <= minWeight) {
DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';); DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
int slot = vrm_->assignVirt2StackSlot(cur->reg); int slot = vrm_->assignVirt2StackSlot(cur->reg);
std::vector<LiveInterval*> added = std::vector<LiveInterval*> added =