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[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.
Summary: In order to support big endian targets for the BuildPairF64 nodes we just need to swap the low/high pair registers. Additionally, for the ExtractElementF64 nodes we have to calculate the correct stack offset with respect to the node's register/operand that we want to extract. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219931 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -325,6 +325,8 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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// We re-use the same spill slot each time so that the stack frame doesn't
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// grow too much in functions with a large number of moves.
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int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
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if (!Subtarget.isLittle())
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std::swap(LoReg, HiReg);
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TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
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0);
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TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
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@@ -369,6 +371,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned N = I->getOperand(2).getImm();
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int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
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// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
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// the cases where mfhc1 is not available). 64-bit architectures and
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@@ -385,7 +388,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
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int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
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TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
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0);
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TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4);
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TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset);
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return true;
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}
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