mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
[PowerPC] Fix and improve vector comparisons
This patch refactors code generation of vector comparisons. This fixes a wrong code-gen bug for ISD::SETGE for floating-point types, and improves generated code for vector comparisons in general. Specifically, the patch moves all logic deciding how to implement vector comparisons into getVCmpInst, which gets two extra boolean outputs indicating to its caller whether its needs to swap the input operands and/or negate the result of the comparison. Apart from implementing these two modifications as directed by getVCmpInst, there is no need to ever implement vector comparisons in any other manner; in particular, there is never a need to perform two separate comparisons (e.g. one for equal and one for greater-than, as code used to do before this patch). Reviewed by Bill Schmidt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214714 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
parent
98b419bff7
commit
3b7a193521
@ -663,94 +663,105 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
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// getVCmpInst: return the vector compare instruction for the specified
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// vector type and condition code. Since this is for altivec specific code,
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// only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
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static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC,
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bool HasVSX) {
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switch (CC) {
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case ISD::SETEQ:
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case ISD::SETUEQ:
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case ISD::SETNE:
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case ISD::SETUNE:
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if (VecVT == MVT::v16i8)
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return PPC::VCMPEQUB;
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else if (VecVT == MVT::v8i16)
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return PPC::VCMPEQUH;
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else if (VecVT == MVT::v4i32)
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return PPC::VCMPEQUW;
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// v4f32 != v4f32 could be translate to unordered not equal
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else if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPEQDP;
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break;
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case ISD::SETLT:
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case ISD::SETGT:
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case ISD::SETLE:
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case ISD::SETGE:
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if (VecVT == MVT::v16i8)
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return PPC::VCMPGTSB;
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else if (VecVT == MVT::v8i16)
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return PPC::VCMPGTSH;
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else if (VecVT == MVT::v4i32)
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return PPC::VCMPGTSW;
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else if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPGTDP;
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break;
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case ISD::SETULT:
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETULE:
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if (VecVT == MVT::v16i8)
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return PPC::VCMPGTUB;
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else if (VecVT == MVT::v8i16)
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return PPC::VCMPGTUH;
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else if (VecVT == MVT::v4i32)
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return PPC::VCMPGTUW;
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break;
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case ISD::SETOEQ:
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if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPEQDP;
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break;
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case ISD::SETOLT:
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case ISD::SETOGT:
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case ISD::SETOLE:
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if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPGTDP;
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break;
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case ISD::SETOGE:
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if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPGEDP;
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break;
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default:
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break;
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}
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llvm_unreachable("Invalid integer vector compare condition");
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}
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static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
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bool HasVSX, bool &Swap, bool &Negate) {
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Swap = false;
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Negate = false;
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// getVCmpEQInst: return the equal compare instruction for the specified vector
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// type. Since this is for altivec specific code, only support the altivec
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// types (v16i8, v8i16, v4i32, and v4f32).
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static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT, bool HasVSX) {
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switch (VecVT) {
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case MVT::v16i8:
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return PPC::VCMPEQUB;
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case MVT::v8i16:
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return PPC::VCMPEQUH;
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case MVT::v4i32:
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return PPC::VCMPEQUW;
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case MVT::v4f32:
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return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
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case MVT::v2f64:
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return PPC::XVCMPEQDP;
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default:
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llvm_unreachable("Invalid integer vector compare condition");
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if (VecVT.isFloatingPoint()) {
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/* Handle some cases by swapping input operands. */
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switch (CC) {
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case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
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case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
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case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
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case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
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case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
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case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
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default: break;
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}
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/* Handle some cases by negating the result. */
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switch (CC) {
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case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
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case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
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case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
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case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
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default: break;
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}
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/* We have instructions implementing the remaining cases. */
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switch (CC) {
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case ISD::SETEQ:
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case ISD::SETOEQ:
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if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPEQDP;
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break;
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case ISD::SETGT:
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case ISD::SETOGT:
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if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPGTDP;
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break;
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case ISD::SETGE:
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case ISD::SETOGE:
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if (VecVT == MVT::v4f32)
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return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
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else if (VecVT == MVT::v2f64)
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return PPC::XVCMPGEDP;
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break;
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default:
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break;
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}
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llvm_unreachable("Invalid floating-point vector compare condition");
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} else {
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/* Handle some cases by swapping input operands. */
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switch (CC) {
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case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
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case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
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case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
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case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
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default: break;
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}
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/* Handle some cases by negating the result. */
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switch (CC) {
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case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
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case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
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case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
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case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
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default: break;
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}
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/* We have instructions implementing the remaining cases. */
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switch (CC) {
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case ISD::SETEQ:
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case ISD::SETUEQ:
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if (VecVT == MVT::v16i8)
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return PPC::VCMPEQUB;
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else if (VecVT == MVT::v8i16)
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return PPC::VCMPEQUH;
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else if (VecVT == MVT::v4i32)
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return PPC::VCMPEQUW;
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break;
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case ISD::SETGT:
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if (VecVT == MVT::v16i8)
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return PPC::VCMPGTSB;
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else if (VecVT == MVT::v8i16)
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return PPC::VCMPGTSH;
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else if (VecVT == MVT::v4i32)
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return PPC::VCMPGTSW;
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break;
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case ISD::SETUGT:
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if (VecVT == MVT::v16i8)
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return PPC::VCMPGTUB;
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else if (VecVT == MVT::v8i16)
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return PPC::VCMPGTUH;
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else if (VecVT == MVT::v4i32)
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return PPC::VCMPGTUW;
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break;
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default:
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break;
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}
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llvm_unreachable("Invalid integer vector compare condition");
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}
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}
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@ -842,60 +853,20 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
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// vector compare operations return the same type as the operands.
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if (LHS.getValueType().isVector()) {
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EVT VecVT = LHS.getValueType();
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MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
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unsigned int VCmpInst = getVCmpInst(VT, CC, PPCSubTarget->hasVSX());
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bool Swap, Negate;
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unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
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PPCSubTarget->hasVSX(), Swap, Negate);
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if (Swap)
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std::swap(LHS, RHS);
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switch (CC) {
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case ISD::SETEQ:
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case ISD::SETOEQ:
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case ISD::SETUEQ:
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return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
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case ISD::SETNE:
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case ISD::SETONE:
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case ISD::SETUNE: {
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SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
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return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
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PPC::VNOR,
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VecVT, VCmp, VCmp);
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}
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case ISD::SETLT:
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case ISD::SETOLT:
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case ISD::SETULT:
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return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
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case ISD::SETGT:
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case ISD::SETOGT:
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case ISD::SETUGT:
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return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
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case ISD::SETGE:
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case ISD::SETOGE:
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case ISD::SETUGE: {
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// Small optimization: Altivec provides a 'Vector Compare Greater Than
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// or Equal To' instruction (vcmpgefp), so in this case there is no
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// need for extra logic for the equal compare.
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if (VecVT.getSimpleVT().isFloatingPoint()) {
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return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
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} else {
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SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
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unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget->hasVSX());
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SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
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return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLOR :
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PPC::VOR,
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VecVT, VCmpGT, VCmpEQ);
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}
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}
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case ISD::SETLE:
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case ISD::SETOLE:
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case ISD::SETULE: {
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SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
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unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget->hasVSX());
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SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
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return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLOR :
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PPC::VOR,
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VecVT, VCmpLE, VCmpEQ);
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}
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default:
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llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
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if (Negate) {
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SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
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return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
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PPC::VNOR,
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VecVT, VCmp, VCmp);
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}
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return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
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}
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if (PPCSubTarget->useCRBits())
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@ -526,11 +526,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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// Altivec does not contain unordered floating-point compare instructions
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setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
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setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
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@ -561,11 +556,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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// Share the Altivec comparison restrictions.
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setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
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setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
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@ -63,9 +63,8 @@ entry:
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ret <16 x i8> %sext
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}
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; CHECK-LABEL: v16si8_cmp_le:
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; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
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; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2
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; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
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; CHECK: vcmpgtsb [[RET:[0-9]+]], 2, 3
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; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
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define <16 x i8> @v16ui8_cmp_le(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
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entry:
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@ -74,9 +73,8 @@ entry:
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ret <16 x i8> %sext
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}
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; CHECK-LABEL: v16ui8_cmp_le:
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; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
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; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2
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; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
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; CHECK: vcmpgtub [[RET:[0-9]+]], 2, 3
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; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
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define <16 x i8> @v16si8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
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entry:
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@ -121,9 +119,8 @@ entry:
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ret <16 x i8> %sext
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}
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; CHECK-LABEL: v16si8_cmp_ge:
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; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
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; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3
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; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
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; CHECK: vcmpgtsb [[RET:[0-9]+]], 3, 2
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; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
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define <16 x i8> @v16ui8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
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entry:
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@ -132,9 +129,8 @@ entry:
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ret <16 x i8> %sext
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}
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; CHECK-LABEL: v16ui8_cmp_ge:
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; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
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; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3
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; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
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; CHECK: vcmpgtub [[RET:[0-9]+]], 3, 2
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; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
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define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
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@ -193,9 +189,8 @@ entry:
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ret <8 x i16> %sext
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}
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; CHECK-LABEL: v8si16_cmp_le:
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; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
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; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2
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; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
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; CHECK: vcmpgtsh [[RET:[0-9]+]], 2, 3
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; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
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define <8 x i16> @v8ui16_cmp_le(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
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entry:
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@ -204,9 +199,8 @@ entry:
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ret <8 x i16> %sext
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}
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; CHECK-LABEL: v8ui16_cmp_le:
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; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
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; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2
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; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
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; CHECK: vcmpgtuh [[RET:[0-9]+]], 2, 3
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; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
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define <8 x i16> @v8si16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
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entry:
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@ -251,9 +245,8 @@ entry:
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ret <8 x i16> %sext
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}
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; CHECK-LABEL: v8si16_cmp_ge:
|
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; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgtsh [[RET:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <8 x i16> @v8ui16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
|
||||
entry:
|
||||
@ -262,9 +255,8 @@ entry:
|
||||
ret <8 x i16> %sext
|
||||
}
|
||||
; CHECK-LABEL: v8ui16_cmp_ge:
|
||||
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgtuh [[RET:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
|
||||
define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
|
||||
@ -326,9 +318,8 @@ entry:
|
||||
ret <4 x i32> %sext
|
||||
}
|
||||
; CHECK-LABEL: v4si32_cmp_le:
|
||||
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgtsw [[RET:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <4 x i32> @v4ui32_cmp_le(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
|
||||
entry:
|
||||
@ -337,9 +328,8 @@ entry:
|
||||
ret <4 x i32> %sext
|
||||
}
|
||||
; CHECK-LABEL: v4ui32_cmp_le:
|
||||
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgtuw [[RET:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <4 x i32> @v4si32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
|
||||
entry:
|
||||
@ -384,9 +374,8 @@ entry:
|
||||
ret <4 x i32> %sext
|
||||
}
|
||||
; CHECK-LABEL: v4si32_cmp_ge:
|
||||
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgtsw [[RET:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <4 x i32> @v4ui32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
|
||||
entry:
|
||||
@ -395,9 +384,8 @@ entry:
|
||||
ret <4 x i32> %sext
|
||||
}
|
||||
; CHECK-LABEL: v4ui32_cmp_ge:
|
||||
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgtuw [[RET:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
|
||||
define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
|
||||
@ -480,9 +468,7 @@ entry:
|
||||
ret <4 x float> %0
|
||||
}
|
||||
; CHECK-LABEL: v4f32_cmp_le:
|
||||
; CHECK: vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
|
||||
; CHECK: vcmpgefp 2, 3, 2
|
||||
|
||||
define <4 x float> @v4f32_cmp_lt(<4 x float> %x, <4 x float> %y) nounwind readnone {
|
||||
entry:
|
||||
@ -514,6 +500,50 @@ entry:
|
||||
; CHECK-LABEL: v4f32_cmp_gt:
|
||||
; CHECK: vcmpgtfp 2, 2, 3
|
||||
|
||||
define <4 x float> @v4f32_cmp_ule(<4 x float> %x, <4 x float> %y) nounwind readnone {
|
||||
entry:
|
||||
%cmp = fcmp ule <4 x float> %x, %y
|
||||
%sext = sext <4 x i1> %cmp to <4 x i32>
|
||||
%0 = bitcast <4 x i32> %sext to <4 x float>
|
||||
ret <4 x float> %0
|
||||
}
|
||||
; CHECK-LABEL: v4f32_cmp_ule:
|
||||
; CHECK: vcmpgtfp [[RET:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <4 x float> @v4f32_cmp_ult(<4 x float> %x, <4 x float> %y) nounwind readnone {
|
||||
entry:
|
||||
%cmp = fcmp ult <4 x float> %x, %y
|
||||
%sext = sext <4 x i1> %cmp to <4 x i32>
|
||||
%0 = bitcast <4 x i32> %sext to <4 x float>
|
||||
ret <4 x float> %0
|
||||
}
|
||||
; CHECK-LABEL: v4f32_cmp_ult:
|
||||
; CHECK: vcmpgefp [[RET:[0-9]+]], 2, 3
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <4 x float> @v4f32_cmp_uge(<4 x float> %x, <4 x float> %y) nounwind readnone {
|
||||
entry:
|
||||
%cmp = fcmp uge <4 x float> %x, %y
|
||||
%sext = sext <4 x i1> %cmp to <4 x i32>
|
||||
%0 = bitcast <4 x i32> %sext to <4 x float>
|
||||
ret <4 x float> %0
|
||||
}
|
||||
; CHECK-LABEL: v4f32_cmp_uge:
|
||||
; CHECK: vcmpgtfp [[RET:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
define <4 x float> @v4f32_cmp_ugt(<4 x float> %x, <4 x float> %y) nounwind readnone {
|
||||
entry:
|
||||
%cmp = fcmp ugt <4 x float> %x, %y
|
||||
%sext = sext <4 x i1> %cmp to <4 x i32>
|
||||
%0 = bitcast <4 x i32> %sext to <4 x float>
|
||||
ret <4 x float> %0
|
||||
}
|
||||
; CHECK-LABEL: v4f32_cmp_ugt:
|
||||
; CHECK: vcmpgefp [[RET:[0-9]+]], 3, 2
|
||||
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
|
||||
|
||||
|
||||
define <8 x float> @v8f32_cmp(<8 x float> %x, <8 x float> %y) nounwind readnone {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user