6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-28 06:32:09 +00:00
Code Issues Projects Releases Wiki Activity

Enclose some variables in a scope to avoid error with some gcc versions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26934 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-22 00:12:37 +00:00
parent 4a7da36546
commit 3b9fa89fca
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -859,7 +859,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
}
break;
case ISD::VEXTRACT_VECTOR_ELT:
case ISD::VEXTRACT_VECTOR_ELT: {
// We know that operand #0 is the Vec vector. If the index is a constant
// or if the invec is a supported hardware type, we can use it. Otherwise,
// lower to a store then an indexed load.
@ -897,10 +897,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// It's now an extract from the appropriate high or low part.
Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2));
} else {
// FIXME: IMPLEMENT STORE/LOAD lowering.
// FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
assert(0 && "unimp!");
}
break;
}
case ISD::CALLSEQ_START: {
SDNode *CallEnd = FindCallEndFromCallStart(Node);