6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

[PowerPC] VSX stores don't also read

Browse Source 
The VSX store instructions were also picking up an implicit "may read" from the
default pattern, which was an intrinsic (and we don't currently have a way of
specifying write-only intrinsics).

This was causing MI verification to fail for VSX spill restores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2015-02-01 19:07:41 +00:00
parent ec716cecda
commit 3bafb64914
3 changed files with 71 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -97,12 +97,12 @@ let Uses = [RM] in {
def STXVD2X : XX1Form<31, 972,
(outs), (ins vsrc:$XT, memrr:$dst),
"stxvd2x $XT, $dst", IIC_LdStSTFD,
[(int_ppc_vsx_stxvd2x v2f64:$XT, xoaddr:$dst)]>;
[(store v2f64:$XT, xoaddr:$dst)]>;
def STXVW4X : XX1Form<31, 908,
(outs), (ins vsrc:$XT, memrr:$dst),
"stxvw4x $XT, $dst", IIC_LdStSTFD,
[(int_ppc_vsx_stxvw4x v4i32:$XT, xoaddr:$dst)]>;
[(store v4i32:$XT, xoaddr:$dst)]>;
}
// Add/Mul Instructions
@ -891,9 +891,11 @@ def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
// Stores.
def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
(STXVD2X $rS, xoaddr:$dst)>;
def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
def : Pat<(store v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
(STXVW4X $rS, xoaddr:$dst)>;
def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
// Permutes.

4
test/CodeGen/PowerPC/vsx-fma-m.ll
View File

@ -269,10 +269,10 @@ entry:
; re-ordering the instructions.
; CHECK-DAG: xvmaddadp [[V1]], 35, 36
; CHECK-DAG: xvmaddmdp 36, 35, 37
; CHECK-DAG: xvmaddmdp 35, 36, 37
; CHECK-DAG: xvmaddadp 34, 35, 38
; CHECK-DAG: stxvd2x 32, 0, 3
; CHECK-DAG: stxvd2x 36, 3, [[C1]]
; CHECK-DAG: stxvd2x 35, 3, [[C1]]
; CHECK-DAG: stxvd2x 34, 3, [[C2]]
; CHECK-DAG: stxvd2x 37, 3, [[C3]]
; CHECK: blr

63
test/CodeGen/PowerPC/vsx-spill-norwstore.ll Normal file
View File

@ -0,0 +1,63 @@
; RUN: llc -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@.str1 = external unnamed_addr constant [5 x i8], align 1
@.str10 = external unnamed_addr constant [9 x i8], align 1
; Function Attrs: nounwind
define void @main() #0 {
; CHECK-LABEL: @main
; Make sure that the stxvd2x passes -verify-machineinstrs
; CHECK: stxvd2x
entry:
%0 = tail call <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
%1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
br i1 false, label %if.then.i68.i, label %check.exit69.i
if.then.i68.i: ; preds = %entry
unreachable
check.exit69.i: ; preds = %entry
br i1 undef, label %if.then.i63.i, label %check.exit64.i
if.then.i63.i: ; preds = %check.exit69.i
tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str10, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8]* @.str1, i64 0, i64 0)) #0
br label %check.exit64.i
check.exit64.i: ; preds = %if.then.i63.i, %check.exit69.i
%2 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %0, <8 x i16> <i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 0, i16 -1, i16 0>) #0
%tobool.i55.i = icmp eq i32 %2, 0
br i1 %tobool.i55.i, label %if.then.i58.i, label %check.exit59.i
if.then.i58.i: ; preds = %check.exit64.i
unreachable
check.exit59.i: ; preds = %check.exit64.i
%3 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %1, <8 x i16> <i16 -1, i16 0, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1>) #0
%tobool.i50.i = icmp eq i32 %3, 0
br i1 %tobool.i50.i, label %if.then.i53.i, label %check.exit54.i
if.then.i53.i: ; preds = %check.exit59.i
unreachable
check.exit54.i: ; preds = %check.exit59.i
unreachable
}
; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8>) #1
; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8>) #1
; Function Attrs: nounwind
declare void @printf(i8* nocapture readonly, ...) #0
; Function Attrs: nounwind readnone
declare i32 @llvm.ppc.altivec.vcmpequh.p(i32, <8 x i16>, <8 x i16>) #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }