diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 52c6b0d8fd4..649068883b8 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -661,7 +661,7 @@ bool LiveIntervals::differingRegisterClasses(unsigned RegA,
   if (MRegisterInfo::isVirtualRegister(RegB))
     return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
   else
-    return RegClass != mri_->getRegClass(RegB);
+    return RegClass->contains(RegB);
 }
 
 bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 8c04cd6e5a2..482325fbff7 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -391,7 +391,7 @@ unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I,
              "PhysReg in PhysRegsUseOrder, but is not allocated?");
       if (PhysRegsUsed[R]) {
         // If the current register is compatible, use it.
-        if (RegInfo->getRegClass(R) == RC) {
+        if (RC->contains(R)) {
           PhysReg = R;
           break;
         } else {
@@ -399,7 +399,7 @@ unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I,
           // compatible, use it.
           for (const unsigned *AliasSet = RegInfo->getAliasSet(R);
                *AliasSet; ++AliasSet) {
-            if (RegInfo->getRegClass(*AliasSet) == RC) {
+            if (RC->contains(*AliasSet)) {
               PhysReg = *AliasSet;    // Take an aliased register
               break;
             }