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[X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags.

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This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-12-24 06:05:22 +00:00
parent 4714bfa1db
commit 3bc4397f1f
8 changed files with 118 additions and 97 deletions
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21
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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@ -328,21 +328,28 @@ namespace X86II {
OpSizeShift = 7,
OpSizeMask = 0x3 << OpSizeShift,
OpSize16 = 1 << OpSizeShift,
OpSize32 = 2 << OpSizeShift,
OpSizeFixed = 0 << OpSizeShift,
OpSize16 = 1 << OpSizeShift,
OpSize32 = 2 << OpSizeShift,
// AsSize - Set if this instruction requires an operand size prefix (0x67),
// which most often indicates that the instruction address 16 bit address
// instead of 32 bit address (or 32 bit address in 64 bit mode).
// AsSize - AdSizeX implies this instruction determines its need of 0x67
// prefix from a normal ModRM memory operand. The other types indicate that
// an operand is encoded with a specific width and a prefix is needed if
// it differs from the current mode.
AdSizeShift = OpSizeShift + 2,
AdSize = 1 << AdSizeShift,
AdSizeMask = 0x3 << AdSizeShift,
AdSizeX = 1 << AdSizeShift,
AdSize16 = 1 << AdSizeShift,
AdSize32 = 2 << AdSizeShift,
AdSize64 = 3 << AdSizeShift,
//===------------------------------------------------------------------===//
// OpPrefix - There are several prefix bytes that are used as opcode
// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
// no prefix.
//
OpPrefixShift = AdSizeShift + 1,
OpPrefixShift = AdSizeShift + 2,
OpPrefixMask = 0x7 << OpPrefixShift,
// PS, PD - Prefix code for packed single and double precision vector

14
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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@ -1199,16 +1199,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
// Emit the address size opcode prefix as needed.
bool need_address_override;
// The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
// should introduce an AdSize16 bit instead of having seven special cases?
if ((!is16BitMode(STI) && TSFlags & X86II::AdSize) ||
(is16BitMode(STI) && (MI.getOpcode() == X86::JECXZ_32 ||
MI.getOpcode() == X86::MOV8o8a ||
MI.getOpcode() == X86::MOV16o16a ||
MI.getOpcode() == X86::MOV32o32a ||
MI.getOpcode() == X86::MOV8ao8 ||
MI.getOpcode() == X86::MOV16ao16 ||
MI.getOpcode() == X86::MOV32ao32))) {
uint64_t AdSize = TSFlags & X86II::AdSizeMask;
if ((is16BitMode(STI) && AdSize == X86II::AdSize32) ||
(is32BitMode(STI) && AdSize == X86II::AdSize16) ||
(is64BitMode(STI) && AdSize == X86II::AdSize32)) {
need_address_override = true;
} else if (MemoryOperand < 0) {
need_address_override = false;

8
lib/Target/X86/X86InstrControl.td
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@ -106,20 +106,20 @@ let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in
// jecxz.
let Uses = [CX] in
def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
"jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[Not64BitMode]>;
"jcxz\t$dst", [], IIC_JCXZ>, AdSize16, Requires<[Not64BitMode]>;
let Uses = [ECX] in
def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
"jecxz\t$dst", [], IIC_JCXZ>, Requires<[Not64BitMode]>;
"jecxz\t$dst", [], IIC_JCXZ>, AdSize32, Requires<[Not64BitMode]>;
// J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
// In 64-bit mode, the address size prefix is jecxz and the unprefixed version
// is jrcxz.
let Uses = [ECX] in
def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
"jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
"jecxz\t$dst", [], IIC_JCXZ>, AdSize32, Requires<[In64BitMode]>;
let Uses = [RCX] in
def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
"jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
"jrcxz\t$dst", [], IIC_JCXZ>, AdSize64, Requires<[In64BitMode]>;
}
// Indirect branches

71
lib/Target/X86/X86InstrFormats.td
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@ -146,11 +146,22 @@ def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
// Address size for encodings that change based on mode.
class AddressSize<bits<2> val> {
bits<2> Value = val;
}
def AdSizeX : AddressSize<0>; // Address size determined using addr operand.
def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
// Prefix byte classes which are used to indicate to the ad-hoc machine code
// emitter that various prefix bytes are required.
class OpSize16 { OperandSize OpSize = OpSize16; }
class OpSize32 { OperandSize OpSize = OpSize32; }
class AdSize { bit hasAdSizePrefix = 1; }
class AdSize16 { AddressSize AdSize = AdSize16; }
class AdSize32 { AddressSize AdSize = AdSize32; }
class AdSize64 { AddressSize AdSize = AdSize64; }
class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; }
class REP { bit hasREPPrefix = 1; }
@ -231,9 +242,11 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
// AsmString from the parser, but still disassemble.
OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
// based on operand size of the mode
// based on operand size of the mode?
bits<2> OpSizeBits = OpSize.Value;
bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
// based on address size of the mode?
bits<2> AdSizeBits = AdSize.Value;
Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
bits<3> OpPrefixBits = OpPrefix.Value;
@ -284,35 +297,35 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
CD8_EltSize,
!srl(VectSize, CD8_Form{1-0}))), 0);
// TSFlags layout should be kept in sync with X86InstrInfo.h.
// TSFlags layout should be kept in sync with X86BaseInfo.h.
let TSFlags{6-0} = FormBits;
let TSFlags{8-7} = OpSizeBits;
let TSFlags{9} = hasAdSizePrefix;
let TSFlags{12-10} = OpPrefixBits;
let TSFlags{15-13} = OpMapBits;
let TSFlags{16} = hasREX_WPrefix;
let TSFlags{20-17} = ImmT.Value;
let TSFlags{23-21} = FPForm.Value;
let TSFlags{24} = hasLockPrefix;
let TSFlags{25} = hasREPPrefix;
let TSFlags{27-26} = ExeDomain.Value;
let TSFlags{29-28} = OpEncBits;
let TSFlags{37-30} = Opcode;
let TSFlags{38} = hasVEX_WPrefix;
let TSFlags{39} = hasVEX_4V;
let TSFlags{40} = hasVEX_4VOp3;
let TSFlags{41} = hasVEX_i8ImmReg;
let TSFlags{42} = hasVEX_L;
let TSFlags{43} = ignoresVEX_L;
let TSFlags{44} = hasEVEX_K;
let TSFlags{45} = hasEVEX_Z;
let TSFlags{46} = hasEVEX_L2;
let TSFlags{47} = hasEVEX_B;
let TSFlags{10-9} = AdSizeBits;
let TSFlags{13-11} = OpPrefixBits;
let TSFlags{16-14} = OpMapBits;
let TSFlags{17} = hasREX_WPrefix;
let TSFlags{21-18} = ImmT.Value;
let TSFlags{24-22} = FPForm.Value;
let TSFlags{25} = hasLockPrefix;
let TSFlags{26} = hasREPPrefix;
let TSFlags{28-27} = ExeDomain.Value;
let TSFlags{30-29} = OpEncBits;
let TSFlags{38-31} = Opcode;
let TSFlags{39} = hasVEX_WPrefix;
let TSFlags{40} = hasVEX_4V;
let TSFlags{41} = hasVEX_4VOp3;
let TSFlags{42} = hasVEX_i8ImmReg;
let TSFlags{43} = hasVEX_L;
let TSFlags{44} = ignoresVEX_L;
let TSFlags{45} = hasEVEX_K;
let TSFlags{46} = hasEVEX_Z;
let TSFlags{47} = hasEVEX_L2;
let TSFlags{48} = hasEVEX_B;
// If we run out of TSFlags bits, it's possible to encode this in 3 bits.
let TSFlags{54-48} = CD8_Scale;
let TSFlags{55} = has3DNow0F0FOpcode;
let TSFlags{56} = hasMemOp4Prefix;
let TSFlags{57} = hasEVEX_RC;
let TSFlags{55-49} = CD8_Scale;
let TSFlags{56} = has3DNow0F0FOpcode;
let TSFlags{57} = hasMemOp4Prefix;
let TSFlags{58} = hasEVEX_RC;
}
class PseudoI<dag oops, dag iops, list<dag> pattern>

84
lib/Target/X86/X86InstrInfo.td
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@ -1241,57 +1241,57 @@ let hasSideEffects = 0 in {
let SchedRW = [WriteALU] in {
let mayLoad = 1 in {
let Defs = [AL] in
def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
def MOV8o8a : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
Requires<[In32BitMode]>;
AdSize32, Requires<[In32BitMode]>;
let Defs = [AX] in
def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
OpSize16, Requires<[In32BitMode]>;
def MOV16o16a : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
OpSize16, AdSize32, Requires<[In32BitMode]>;
let Defs = [EAX] in
def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
OpSize32, Requires<[In32BitMode]>;
def MOV32o32a : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
OpSize32, AdSize32, Requires<[In32BitMode]>;
let Defs = [AL] in
def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
AdSize, Requires<[In16BitMode]>;
def MOV8o8a_16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
AdSize16, Requires<[In16BitMode]>;
let Defs = [AX] in
def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
OpSize16, AdSize, Requires<[In16BitMode]>;
def MOV16o16a_16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
OpSize16, AdSize16, Requires<[In16BitMode]>;
let Defs = [EAX] in
def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
AdSize, OpSize32, Requires<[In16BitMode]>;
def MOV32o32a_16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
AdSize16, OpSize32, Requires<[In16BitMode]>;
}
let mayStore = 1 in {
let Uses = [AL] in
def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
def MOV8ao8 : Ii32<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
Requires<[In32BitMode]>;
AdSize32, Requires<[In32BitMode]>;
let Uses = [AX] in
def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
OpSize16, Requires<[In32BitMode]>;
def MOV16ao16 : Ii32<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
OpSize16, AdSize32, Requires<[In32BitMode]>;
let Uses = [EAX] in
def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
OpSize32, Requires<[In32BitMode]>;
def MOV32ao32 : Ii32<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
OpSize32, AdSize32, Requires<[In32BitMode]>;
let Uses = [AL] in
def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
AdSize, Requires<[In16BitMode]>;
def MOV8ao8_16 : Ii16<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
AdSize16, Requires<[In16BitMode]>;
let Uses = [AX] in
def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
OpSize16, AdSize, Requires<[In16BitMode]>;
def MOV16ao16_16 : Ii16<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
OpSize16, AdSize16, Requires<[In16BitMode]>;
let Uses = [EAX] in
def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
OpSize32, AdSize, Requires<[In16BitMode]>;
def MOV32ao32_16 : Ii16<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
OpSize32, AdSize16, Requires<[In16BitMode]>;
}
}
@ -1301,38 +1301,38 @@ let mayLoad = 1 in {
let Defs = [AL] in
def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
"movabs{b}\t{$src, %al|al, $src}", []>,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
let Defs = [AX] in
def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
let Defs = [EAX] in
def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
"movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
let Defs = [RAX] in
def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
"movabs{q}\t{$src, %rax|rax, $src}", []>,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
}
let mayStore = 1 in {
let Uses = [AL] in
def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
"movabs{b}\t{%al, $dst|$dst, al}", []>,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
let Uses = [AX] in
def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
let Uses = [EAX] in
def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
"movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
let Uses = [RAX] in
def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
"movabs{q}\t{%rax, $dst|$dst, rax}", []>,
Requires<[In64BitMode]>;
AdSize64, Requires<[In64BitMode]>;
}
} // hasSideEffects = 0

3
utils/TableGen/X86DisassemblerTables.cpp
View File

@ -822,6 +822,9 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision,
InstructionSpecifier &previousInfo =
InstructionSpecifiers[decision.instructionIDs[index]];
// FIXME this doesn't actually work. The MCInsts the disassembler
// create don't encode re-encode correctly. They just manage to mostly
// print correctly.
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
// presence of the AdSize prefix. However, the disassembler doesn't
// care about that difference in the instruction definition; it

10
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -119,6 +119,10 @@ namespace X86Local {
enum {
OpSize16 = 1, OpSize32 = 2
};
enum {
AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
};
}
using namespace X86Disassembler;
@ -194,7 +198,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
Encoding = byteFromRec(Rec, "OpEncBits");
OpSize = byteFromRec(Rec, "OpSizeBits");
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
AdSize = byteFromRec(Rec, "AdSizeBits");
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
@ -410,7 +414,7 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_64BIT_XS_OPSIZE;
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
insnContext = IC_64BIT_OPSIZE;
else if (HasAdSizePrefix)
else if (AdSize == X86Local::AdSize32)
insnContext = IC_64BIT_ADSIZE;
else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
insnContext = IC_64BIT_REXW_XS;
@ -431,7 +435,7 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_XS_OPSIZE;
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
insnContext = IC_OPSIZE;
else if (HasAdSizePrefix)
else if (AdSize == X86Local::AdSize16)
insnContext = IC_ADSIZE;
else if (OpPrefix == X86Local::XD)
insnContext = IC_XD;

4
utils/TableGen/X86RecognizableInstr.h
View File

@ -50,8 +50,8 @@ private:
uint8_t Encoding;
/// The OpSize field from the record
uint8_t OpSize;
/// The hasAdSizePrefix field from the record
bool HasAdSizePrefix;
/// The AdSize field from the record
uint8_t AdSize;
/// The hasREX_WPrefix field from the record
bool HasREX_WPrefix;
/// The hasVEX_4V field from the record