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[X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags.
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224809 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -328,21 +328,28 @@ namespace X86II {
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OpSizeShift = 7,
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OpSizeShift = 7,
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OpSizeMask = 0x3 << OpSizeShift,
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OpSizeMask = 0x3 << OpSizeShift,
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OpSizeFixed = 0 << OpSizeShift,
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OpSize16 = 1 << OpSizeShift,
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OpSize16 = 1 << OpSizeShift,
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OpSize32 = 2 << OpSizeShift,
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OpSize32 = 2 << OpSizeShift,
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// AsSize - AdSizeX implies this instruction determines its need of 0x67
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// which most often indicates that the instruction address 16 bit address
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// prefix from a normal ModRM memory operand. The other types indicate that
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// instead of 32 bit address (or 32 bit address in 64 bit mode).
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// an operand is encoded with a specific width and a prefix is needed if
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// it differs from the current mode.
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AdSizeShift = OpSizeShift + 2,
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AdSizeShift = OpSizeShift + 2,
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AdSize = 1 << AdSizeShift,
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AdSizeMask = 0x3 << AdSizeShift,
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AdSizeX = 1 << AdSizeShift,
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AdSize16 = 1 << AdSizeShift,
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AdSize32 = 2 << AdSizeShift,
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AdSize64 = 3 << AdSizeShift,
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//===------------------------------------------------------------------===//
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//===------------------------------------------------------------------===//
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// OpPrefix - There are several prefix bytes that are used as opcode
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// OpPrefix - There are several prefix bytes that are used as opcode
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// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
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// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
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// no prefix.
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// no prefix.
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//
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//
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OpPrefixShift = AdSizeShift + 1,
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OpPrefixShift = AdSizeShift + 2,
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OpPrefixMask = 0x7 << OpPrefixShift,
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OpPrefixMask = 0x7 << OpPrefixShift,
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// PS, PD - Prefix code for packed single and double precision vector
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// PS, PD - Prefix code for packed single and double precision vector
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@ -1199,16 +1199,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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// Emit the address size opcode prefix as needed.
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// Emit the address size opcode prefix as needed.
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bool need_address_override;
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bool need_address_override;
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// The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
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uint64_t AdSize = TSFlags & X86II::AdSizeMask;
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// should introduce an AdSize16 bit instead of having seven special cases?
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if ((is16BitMode(STI) && AdSize == X86II::AdSize32) ||
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if ((!is16BitMode(STI) && TSFlags & X86II::AdSize) ||
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(is32BitMode(STI) && AdSize == X86II::AdSize16) ||
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(is16BitMode(STI) && (MI.getOpcode() == X86::JECXZ_32 ||
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(is64BitMode(STI) && AdSize == X86II::AdSize32)) {
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MI.getOpcode() == X86::MOV8o8a ||
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MI.getOpcode() == X86::MOV16o16a ||
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MI.getOpcode() == X86::MOV32o32a ||
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MI.getOpcode() == X86::MOV8ao8 ||
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MI.getOpcode() == X86::MOV16ao16 ||
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MI.getOpcode() == X86::MOV32ao32))) {
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need_address_override = true;
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need_address_override = true;
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} else if (MemoryOperand < 0) {
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} else if (MemoryOperand < 0) {
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need_address_override = false;
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need_address_override = false;
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@ -106,20 +106,20 @@ let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in
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// jecxz.
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// jecxz.
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let Uses = [CX] in
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let Uses = [CX] in
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def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[Not64BitMode]>;
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"jcxz\t$dst", [], IIC_JCXZ>, AdSize16, Requires<[Not64BitMode]>;
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let Uses = [ECX] in
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let Uses = [ECX] in
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def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jecxz\t$dst", [], IIC_JCXZ>, Requires<[Not64BitMode]>;
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"jecxz\t$dst", [], IIC_JCXZ>, AdSize32, Requires<[Not64BitMode]>;
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// J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
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// J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
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// In 64-bit mode, the address size prefix is jecxz and the unprefixed version
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// In 64-bit mode, the address size prefix is jecxz and the unprefixed version
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// is jrcxz.
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// is jrcxz.
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let Uses = [ECX] in
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let Uses = [ECX] in
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def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
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"jecxz\t$dst", [], IIC_JCXZ>, AdSize32, Requires<[In64BitMode]>;
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let Uses = [RCX] in
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let Uses = [RCX] in
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def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
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"jrcxz\t$dst", [], IIC_JCXZ>, AdSize64, Requires<[In64BitMode]>;
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}
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}
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// Indirect branches
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// Indirect branches
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@ -146,11 +146,22 @@ def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
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def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
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def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
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def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
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def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
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// Address size for encodings that change based on mode.
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class AddressSize<bits<2> val> {
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bits<2> Value = val;
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}
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def AdSizeX : AddressSize<0>; // Address size determined using addr operand.
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def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
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def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
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def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// emitter that various prefix bytes are required.
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// emitter that various prefix bytes are required.
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class OpSize16 { OperandSize OpSize = OpSize16; }
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class OpSize16 { OperandSize OpSize = OpSize16; }
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class OpSize32 { OperandSize OpSize = OpSize32; }
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class OpSize32 { OperandSize OpSize = OpSize32; }
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class AdSize { bit hasAdSizePrefix = 1; }
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class AdSize16 { AddressSize AdSize = AdSize16; }
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class AdSize32 { AddressSize AdSize = AdSize32; }
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class AdSize64 { AddressSize AdSize = AdSize64; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class REP { bit hasREPPrefix = 1; }
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class REP { bit hasREPPrefix = 1; }
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@ -231,9 +242,11 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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// AsmString from the parser, but still disassemble.
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// AsmString from the parser, but still disassemble.
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OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
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OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
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// based on operand size of the mode
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// based on operand size of the mode?
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bits<2> OpSizeBits = OpSize.Value;
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bits<2> OpSizeBits = OpSize.Value;
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bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
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AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
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// based on address size of the mode?
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bits<2> AdSizeBits = AdSize.Value;
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Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
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Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
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bits<3> OpPrefixBits = OpPrefix.Value;
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bits<3> OpPrefixBits = OpPrefix.Value;
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@ -284,35 +297,35 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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CD8_EltSize,
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CD8_EltSize,
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!srl(VectSize, CD8_Form{1-0}))), 0);
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!srl(VectSize, CD8_Form{1-0}))), 0);
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// TSFlags layout should be kept in sync with X86InstrInfo.h.
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// TSFlags layout should be kept in sync with X86BaseInfo.h.
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let TSFlags{6-0} = FormBits;
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let TSFlags{6-0} = FormBits;
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let TSFlags{8-7} = OpSizeBits;
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let TSFlags{8-7} = OpSizeBits;
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let TSFlags{9} = hasAdSizePrefix;
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let TSFlags{10-9} = AdSizeBits;
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let TSFlags{12-10} = OpPrefixBits;
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let TSFlags{13-11} = OpPrefixBits;
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let TSFlags{15-13} = OpMapBits;
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let TSFlags{16-14} = OpMapBits;
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let TSFlags{16} = hasREX_WPrefix;
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let TSFlags{17} = hasREX_WPrefix;
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let TSFlags{20-17} = ImmT.Value;
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let TSFlags{21-18} = ImmT.Value;
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let TSFlags{23-21} = FPForm.Value;
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let TSFlags{24-22} = FPForm.Value;
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let TSFlags{24} = hasLockPrefix;
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let TSFlags{25} = hasLockPrefix;
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let TSFlags{25} = hasREPPrefix;
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let TSFlags{26} = hasREPPrefix;
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let TSFlags{27-26} = ExeDomain.Value;
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let TSFlags{28-27} = ExeDomain.Value;
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let TSFlags{29-28} = OpEncBits;
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let TSFlags{30-29} = OpEncBits;
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let TSFlags{37-30} = Opcode;
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let TSFlags{38-31} = Opcode;
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let TSFlags{38} = hasVEX_WPrefix;
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let TSFlags{39} = hasVEX_WPrefix;
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let TSFlags{39} = hasVEX_4V;
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let TSFlags{40} = hasVEX_4V;
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let TSFlags{40} = hasVEX_4VOp3;
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let TSFlags{41} = hasVEX_4VOp3;
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let TSFlags{41} = hasVEX_i8ImmReg;
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let TSFlags{42} = hasVEX_i8ImmReg;
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let TSFlags{42} = hasVEX_L;
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let TSFlags{43} = hasVEX_L;
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let TSFlags{43} = ignoresVEX_L;
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let TSFlags{44} = ignoresVEX_L;
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let TSFlags{44} = hasEVEX_K;
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let TSFlags{45} = hasEVEX_K;
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let TSFlags{45} = hasEVEX_Z;
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let TSFlags{46} = hasEVEX_Z;
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let TSFlags{46} = hasEVEX_L2;
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let TSFlags{47} = hasEVEX_L2;
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let TSFlags{47} = hasEVEX_B;
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let TSFlags{48} = hasEVEX_B;
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// If we run out of TSFlags bits, it's possible to encode this in 3 bits.
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// If we run out of TSFlags bits, it's possible to encode this in 3 bits.
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let TSFlags{54-48} = CD8_Scale;
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let TSFlags{55-49} = CD8_Scale;
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let TSFlags{55} = has3DNow0F0FOpcode;
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let TSFlags{56} = has3DNow0F0FOpcode;
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let TSFlags{56} = hasMemOp4Prefix;
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let TSFlags{57} = hasMemOp4Prefix;
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let TSFlags{57} = hasEVEX_RC;
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let TSFlags{58} = hasEVEX_RC;
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}
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}
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class PseudoI<dag oops, dag iops, list<dag> pattern>
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class PseudoI<dag oops, dag iops, list<dag> pattern>
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@ -1243,55 +1243,55 @@ let mayLoad = 1 in {
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let Defs = [AL] in
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let Defs = [AL] in
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def MOV8o8a : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
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def MOV8o8a : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
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"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
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"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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AdSize32, Requires<[In32BitMode]>;
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let Defs = [AX] in
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let Defs = [AX] in
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def MOV16o16a : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
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def MOV16o16a : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
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"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
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"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
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OpSize16, Requires<[In32BitMode]>;
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OpSize16, AdSize32, Requires<[In32BitMode]>;
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let Defs = [EAX] in
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let Defs = [EAX] in
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def MOV32o32a : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
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def MOV32o32a : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
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"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
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"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
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OpSize32, Requires<[In32BitMode]>;
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OpSize32, AdSize32, Requires<[In32BitMode]>;
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let Defs = [AL] in
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let Defs = [AL] in
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def MOV8o8a_16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
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def MOV8o8a_16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
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"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
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"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
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AdSize, Requires<[In16BitMode]>;
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AdSize16, Requires<[In16BitMode]>;
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let Defs = [AX] in
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let Defs = [AX] in
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def MOV16o16a_16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
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def MOV16o16a_16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
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"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
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"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
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OpSize16, AdSize, Requires<[In16BitMode]>;
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OpSize16, AdSize16, Requires<[In16BitMode]>;
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let Defs = [EAX] in
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let Defs = [EAX] in
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def MOV32o32a_16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
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def MOV32o32a_16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
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"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
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"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
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AdSize, OpSize32, Requires<[In16BitMode]>;
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AdSize16, OpSize32, Requires<[In16BitMode]>;
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}
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}
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let mayStore = 1 in {
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let mayStore = 1 in {
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let Uses = [AL] in
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let Uses = [AL] in
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def MOV8ao8 : Ii32<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
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def MOV8ao8 : Ii32<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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AdSize32, Requires<[In32BitMode]>;
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let Uses = [AX] in
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let Uses = [AX] in
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def MOV16ao16 : Ii32<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
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def MOV16ao16 : Ii32<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
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OpSize16, Requires<[In32BitMode]>;
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OpSize16, AdSize32, Requires<[In32BitMode]>;
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let Uses = [EAX] in
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let Uses = [EAX] in
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def MOV32ao32 : Ii32<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
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def MOV32ao32 : Ii32<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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OpSize32, Requires<[In32BitMode]>;
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OpSize32, AdSize32, Requires<[In32BitMode]>;
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let Uses = [AL] in
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let Uses = [AL] in
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def MOV8ao8_16 : Ii16<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
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def MOV8ao8_16 : Ii16<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
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AdSize, Requires<[In16BitMode]>;
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AdSize16, Requires<[In16BitMode]>;
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let Uses = [AX] in
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let Uses = [AX] in
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def MOV16ao16_16 : Ii16<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
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def MOV16ao16_16 : Ii16<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
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OpSize16, AdSize, Requires<[In16BitMode]>;
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OpSize16, AdSize16, Requires<[In16BitMode]>;
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let Uses = [EAX] in
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let Uses = [EAX] in
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def MOV32ao32_16 : Ii16<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
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def MOV32ao32_16 : Ii16<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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OpSize32, AdSize, Requires<[In16BitMode]>;
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OpSize32, AdSize16, Requires<[In16BitMode]>;
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||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1301,38 +1301,38 @@ let mayLoad = 1 in {
|
|||||||
let Defs = [AL] in
|
let Defs = [AL] in
|
||||||
def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
|
def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
|
||||||
"movabs{b}\t{$src, %al|al, $src}", []>,
|
"movabs{b}\t{$src, %al|al, $src}", []>,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
let Defs = [AX] in
|
let Defs = [AX] in
|
||||||
def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
|
def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
|
||||||
"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
|
"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
let Defs = [EAX] in
|
let Defs = [EAX] in
|
||||||
def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
|
def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
|
||||||
"movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
|
"movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
let Defs = [RAX] in
|
let Defs = [RAX] in
|
||||||
def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
|
def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
|
||||||
"movabs{q}\t{$src, %rax|rax, $src}", []>,
|
"movabs{q}\t{$src, %rax|rax, $src}", []>,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
}
|
}
|
||||||
|
|
||||||
let mayStore = 1 in {
|
let mayStore = 1 in {
|
||||||
let Uses = [AL] in
|
let Uses = [AL] in
|
||||||
def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
|
def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
|
||||||
"movabs{b}\t{%al, $dst|$dst, al}", []>,
|
"movabs{b}\t{%al, $dst|$dst, al}", []>,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
let Uses = [AX] in
|
let Uses = [AX] in
|
||||||
def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
|
def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
|
||||||
"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
|
"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
let Uses = [EAX] in
|
let Uses = [EAX] in
|
||||||
def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
|
def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
|
||||||
"movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
|
"movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
let Uses = [RAX] in
|
let Uses = [RAX] in
|
||||||
def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
|
def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
|
||||||
"movabs{q}\t{%rax, $dst|$dst, rax}", []>,
|
"movabs{q}\t{%rax, $dst|$dst, rax}", []>,
|
||||||
Requires<[In64BitMode]>;
|
AdSize64, Requires<[In64BitMode]>;
|
||||||
}
|
}
|
||||||
} // hasSideEffects = 0
|
} // hasSideEffects = 0
|
||||||
|
|
||||||
|
@ -822,6 +822,9 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision,
|
|||||||
InstructionSpecifier &previousInfo =
|
InstructionSpecifier &previousInfo =
|
||||||
InstructionSpecifiers[decision.instructionIDs[index]];
|
InstructionSpecifiers[decision.instructionIDs[index]];
|
||||||
|
|
||||||
|
// FIXME this doesn't actually work. The MCInsts the disassembler
|
||||||
|
// create don't encode re-encode correctly. They just manage to mostly
|
||||||
|
// print correctly.
|
||||||
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
|
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
|
||||||
// presence of the AdSize prefix. However, the disassembler doesn't
|
// presence of the AdSize prefix. However, the disassembler doesn't
|
||||||
// care about that difference in the instruction definition; it
|
// care about that difference in the instruction definition; it
|
||||||
|
@ -119,6 +119,10 @@ namespace X86Local {
|
|||||||
enum {
|
enum {
|
||||||
OpSize16 = 1, OpSize32 = 2
|
OpSize16 = 1, OpSize32 = 2
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
|
||||||
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
using namespace X86Disassembler;
|
using namespace X86Disassembler;
|
||||||
@ -194,7 +198,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
|
|||||||
Encoding = byteFromRec(Rec, "OpEncBits");
|
Encoding = byteFromRec(Rec, "OpEncBits");
|
||||||
|
|
||||||
OpSize = byteFromRec(Rec, "OpSizeBits");
|
OpSize = byteFromRec(Rec, "OpSizeBits");
|
||||||
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
|
AdSize = byteFromRec(Rec, "AdSizeBits");
|
||||||
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
|
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
|
||||||
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
|
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
|
||||||
HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
|
HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
|
||||||
@ -410,7 +414,7 @@ InstructionContext RecognizableInstr::insnContext() const {
|
|||||||
insnContext = IC_64BIT_XS_OPSIZE;
|
insnContext = IC_64BIT_XS_OPSIZE;
|
||||||
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
||||||
insnContext = IC_64BIT_OPSIZE;
|
insnContext = IC_64BIT_OPSIZE;
|
||||||
else if (HasAdSizePrefix)
|
else if (AdSize == X86Local::AdSize32)
|
||||||
insnContext = IC_64BIT_ADSIZE;
|
insnContext = IC_64BIT_ADSIZE;
|
||||||
else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
|
else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
|
||||||
insnContext = IC_64BIT_REXW_XS;
|
insnContext = IC_64BIT_REXW_XS;
|
||||||
@ -431,7 +435,7 @@ InstructionContext RecognizableInstr::insnContext() const {
|
|||||||
insnContext = IC_XS_OPSIZE;
|
insnContext = IC_XS_OPSIZE;
|
||||||
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
||||||
insnContext = IC_OPSIZE;
|
insnContext = IC_OPSIZE;
|
||||||
else if (HasAdSizePrefix)
|
else if (AdSize == X86Local::AdSize16)
|
||||||
insnContext = IC_ADSIZE;
|
insnContext = IC_ADSIZE;
|
||||||
else if (OpPrefix == X86Local::XD)
|
else if (OpPrefix == X86Local::XD)
|
||||||
insnContext = IC_XD;
|
insnContext = IC_XD;
|
||||||
|
@ -50,8 +50,8 @@ private:
|
|||||||
uint8_t Encoding;
|
uint8_t Encoding;
|
||||||
/// The OpSize field from the record
|
/// The OpSize field from the record
|
||||||
uint8_t OpSize;
|
uint8_t OpSize;
|
||||||
/// The hasAdSizePrefix field from the record
|
/// The AdSize field from the record
|
||||||
bool HasAdSizePrefix;
|
uint8_t AdSize;
|
||||||
/// The hasREX_WPrefix field from the record
|
/// The hasREX_WPrefix field from the record
|
||||||
bool HasREX_WPrefix;
|
bool HasREX_WPrefix;
|
||||||
/// The hasVEX_4V field from the record
|
/// The hasVEX_4V field from the record
|
||||||
|
Loading…
Reference in New Issue
Block a user