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Implement some dag combines that allow doing fneg/fabs/fcopysign in integer
registers if used by a bitconvert or using a bitconvert. This allows us to avoid constant pool loads and use cheaper integer instructions when the values come from or end up in integer regs anyway. For example, we now compile CodeGen/X86/fp-in-intregs.ll to: _test1: movl $2147483648, %eax xorl 4(%esp), %eax ret _test2: movl $1065353216, %eax orl 4(%esp), %eax andl $3212836864, %eax ret Instead of: _test1: movss 4(%esp), %xmm0 xorps LCPI2_0, %xmm0 movd %xmm0, %eax ret _test2: movss 4(%esp), %xmm0 andps LCPI3_0, %xmm0 movss LCPI3_1, %xmm1 andps LCPI3_2, %xmm1 orps %xmm0, %xmm1 movd %xmm1, %eax ret bitconverts can happen due to various calling conventions that require fp values to passed in integer regs in some cases, e.g. when returning a complex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46414 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1190,7 +1190,7 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
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return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
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return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
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// If we know the sign bits of both operands are zero, strength reduce to a
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// If we know the sign bits of both operands are zero, strength reduce to a
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// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
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// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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if (DAG.MaskedValueIsZero(N1, SignBit) &&
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if (DAG.MaskedValueIsZero(N1, SignBit) &&
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DAG.MaskedValueIsZero(N0, SignBit))
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DAG.MaskedValueIsZero(N0, SignBit))
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return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
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return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
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@ -1306,7 +1306,7 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) {
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return DAG.getNode(ISD::SREM, VT, N0, N1);
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return DAG.getNode(ISD::SREM, VT, N0, N1);
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// If we know the sign bits of both operands are zero, strength reduce to a
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// If we know the sign bits of both operands are zero, strength reduce to a
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// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
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// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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if (DAG.MaskedValueIsZero(N1, SignBit) &&
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if (DAG.MaskedValueIsZero(N1, SignBit) &&
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DAG.MaskedValueIsZero(N0, SignBit))
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DAG.MaskedValueIsZero(N0, SignBit))
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return DAG.getNode(ISD::UREM, VT, N0, N1);
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return DAG.getNode(ISD::UREM, VT, N0, N1);
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@ -3276,6 +3276,57 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
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}
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}
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}
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}
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// Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit)
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// Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
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// This often reduces constant pool loads.
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if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
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N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) {
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SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
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AddToWorkList(NewConv.Val);
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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if (N0.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
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assert(N0.getOpcode() == ISD::FABS);
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return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT));
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}
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// Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
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// Note that we don't handle copysign(x,cst) because this can always be folded
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// to an fneg or fabs.
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if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
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isa<ConstantFPSDNode>(N0.getOperand(0))) {
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unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType());
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SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth),
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N0.getOperand(1));
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AddToWorkList(X.Val);
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// If X has a different width than the result/lhs, sext it or truncate it.
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unsigned VTWidth = MVT::getSizeInBits(VT);
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if (OrigXWidth < VTWidth) {
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X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
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AddToWorkList(X.Val);
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} else if (OrigXWidth > VTWidth) {
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// To get the sign bit in the right place, we have to shift it right
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// before truncating.
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X = DAG.getNode(ISD::SRL, X.getValueType(), X,
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DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
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AddToWorkList(X.Val);
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X = DAG.getNode(ISD::TRUNCATE, VT, X);
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AddToWorkList(X.Val);
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}
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
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AddToWorkList(X.Val);
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SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
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Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
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AddToWorkList(Cst.Val);
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return DAG.getNode(ISD::OR, VT, X, Cst);
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}
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return SDOperand();
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return SDOperand();
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}
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}
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@ -3732,6 +3783,19 @@ SDOperand DAGCombiner::visitFNEG(SDNode *N) {
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if (isNegatibleForFree(N0))
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if (isNegatibleForFree(N0))
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return GetNegatedExpression(N0, DAG);
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return GetNegatedExpression(N0, DAG);
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// Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
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// constant pool values.
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if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse()) {
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SDOperand Int = N0.getOperand(0);
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MVT::ValueType IntVT = Int.getValueType();
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if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
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Int = DAG.getNode(ISD::XOR, IntVT, Int,
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DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT));
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AddToWorkList(Int.Val);
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return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
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}
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}
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return SDOperand();
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return SDOperand();
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}
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}
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@ -3751,6 +3815,19 @@ SDOperand DAGCombiner::visitFABS(SDNode *N) {
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if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
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if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
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return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
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return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
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// Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
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// constant pool values.
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if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse()) {
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SDOperand Int = N0.getOperand(0);
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MVT::ValueType IntVT = Int.getValueType();
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if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
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Int = DAG.getNode(ISD::AND, IntVT, Int,
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DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT));
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AddToWorkList(Int.Val);
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return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
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}
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}
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return SDOperand();
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return SDOperand();
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}
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}
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21
test/CodeGen/X86/fp-in-intregs.ll
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21
test/CodeGen/X86/fp-in-intregs.ll
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@ -0,0 +1,21 @@
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; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not egrep {\(\(xor\|and\)ps\|movd\)}
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; These operations should be done in integer registers, eliminating constant
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; pool loads, movd's etc.
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define i32 @test1(float %x) nounwind {
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entry:
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%tmp2 = sub float -0.000000e+00, %x ; <float> [#uses=1]
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%tmp210 = bitcast float %tmp2 to i32 ; <i32> [#uses=1]
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ret i32 %tmp210
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}
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define i32 @test2(float %x) nounwind {
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entry:
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%tmp2 = tail call float @copysignf( float 1.000000e+00, float %x ) nounwind readnone ; <float> [#uses=1]
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%tmp210 = bitcast float %tmp2 to i32 ; <i32> [#uses=1]
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ret i32 %tmp210
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}
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declare float @copysignf(float, float) nounwind readnone
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