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Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201718 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1556,6 +1556,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::UMULO, MVT::i64, Custom);
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setOperationAction(ISD::SMULO, MVT::i64, Custom);
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setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
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}
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
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14
test/CodeGen/SPARC/parts.ll
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14
test/CodeGen/SPARC/parts.ll
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@ -0,0 +1,14 @@
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; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; CHECK-LABEL: test
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; CHECK: srl %i1, 0, %o2
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; CHECK-NEXT: or %g0, %i2, %o0
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; CHECK-NEXT: call __ashlti3
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; CHECK-NEXT: or %g0, %i3, %o1
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; CHECK-NEXT: or %g0, %o0, %i0
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define i128 @test(i128 %a, i128 %b) {
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entry:
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%tmp = shl i128 %b, %a
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ret i128 %tmp
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}
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