From 3bda20112e2c8bf583eddb3c08da1b0d7455baee Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 12 Jan 2010 18:31:19 +0000 Subject: [PATCH] Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93245 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86Instr64bit.td | 8 +++++--- lib/Target/X86/X86InstrInfo.td | 27 ++++++++------------------- 2 files changed, 13 insertions(+), 22 deletions(-) diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index d67a48291e2..08e1dd1e060 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1093,7 +1093,7 @@ let isCommutable = 1 in def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "or{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (or_not_add GR64:$src1, GR64:$src2)), + [(set GR64:$dst, (or GR64:$src1, GR64:$src2)), (implicit EFLAGS)]>; def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), @@ -1106,12 +1106,12 @@ def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "or{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (or_not_add GR64:$src1, i64immSExt8:$src2)), + [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)), (implicit EFLAGS)]>; def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "or{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (or_not_add GR64:$src1, i64immSExt32:$src2)), + [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)), (implicit EFLAGS)]>; } // isTwoAddress @@ -2130,6 +2130,7 @@ def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1), (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>; // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. +let AddedComplexity = 5 in { // Try this before the selecting to OR def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2), (implicit EFLAGS)), (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; @@ -2139,6 +2140,7 @@ def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2), def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2), (implicit EFLAGS)), (ADD64rr GR64:$src1, GR64:$src2)>; +} // AddedComplexity // X86 specific add which produces a flag. def : Pat<(addc GR64:$src1, GR64:$src2), diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index aac9f38c8a9..396cb53502e 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -507,19 +507,6 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ return (~KnownZero0 & ~KnownZero1) == 0; } }]>; -def or_not_add : PatFrag<(ops node:$lhs, node:$rhs),(or node:$lhs, node:$rhs),[{ - if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) - return !CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); - else { - unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); - APInt Mask = APInt::getAllOnesValue(BitWidth); - APInt KnownZero0, KnownOne0; - CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0); - APInt KnownZero1, KnownOne1; - CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0); - return (~KnownZero0 & ~KnownZero1) != 0; - } -}]>; // 'shld' and 'shrd' instruction patterns. Note that even though these have // the srl and shl in their patterns, the C++ code must still check for them, @@ -1869,12 +1856,12 @@ def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "or{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (or_not_add GR16:$src1, GR16:$src2)), + [(set GR16:$dst, (or GR16:$src1, GR16:$src2)), (implicit EFLAGS)]>, OpSize; def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "or{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (or_not_add GR32:$src1, GR32:$src2)), + [(set GR32:$dst, (or GR32:$src1, GR32:$src2)), (implicit EFLAGS)]>; } @@ -1913,23 +1900,23 @@ def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "or{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (or_not_add GR16:$src1, imm:$src2)), + [(set GR16:$dst, (or GR16:$src1, imm:$src2)), (implicit EFLAGS)]>, OpSize; def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "or{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (or_not_add GR32:$src1, imm:$src2)), + [(set GR32:$dst, (or GR32:$src1, imm:$src2)), (implicit EFLAGS)]>; def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "or{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (or_not_add GR16:$src1, i16immSExt8:$src2)), + [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)), (implicit EFLAGS)]>, OpSize; def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "or{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (or_not_add GR32:$src1, i32immSExt8:$src2)), + [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)), (implicit EFLAGS)]>; let isTwoAddress = 0 in { def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), @@ -4679,6 +4666,7 @@ def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), (SETB_C32r)>; // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. +let AddedComplexity = 5 in { // Try this before the selecting to OR def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2), (implicit EFLAGS)), (ADD16ri GR16:$src1, imm:$src2)>; @@ -4697,6 +4685,7 @@ def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2), def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2), (implicit EFLAGS)), (ADD32rr GR32:$src1, GR32:$src2)>; +} // AddedComplexity //===----------------------------------------------------------------------===// // EFLAGS-defining Patterns