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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115494 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -645,21 +645,6 @@ release includes a few major enhancements and additions to the optimizers:</p>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="executionengine">Interpreter and JIT Improvements</a>
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</div>
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<div class="doc_text">
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<ul>
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<li></li>
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</ul>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="mc">MC Level Improvements</a>
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@ -689,9 +674,9 @@ in.</p>
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<li>The MC disassembler now fully supports ARM and Thumb. ARM assembler support
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is still in early development though.</li>
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<li>The X86 MC assembler now supports the X86 AES and AVX instruction set.</li>
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<li>Work on ELF and COFF support is well underway, but isn't useful yet in LLVM
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2.8. Please contact the llvmdev mailing list if you're interested in
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this.</li>
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<li>Work on ELF and COFF object files and ARM target support is well underway,
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but isn't useful yet in LLVM 2.8. Please contact the llvmdev mailing list
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if you're interested in this.</li>
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</ul>
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<p>For more information, please see the <a
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@ -702,7 +687,6 @@ LLVM MC Project Blog Post</a>.
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="codegen">Target Independent Code Generator Improvements</a>
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@ -715,35 +699,57 @@ infrastructure, which allows us to implement more aggressive algorithms and make
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it run faster:</p>
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<ul>
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<li></li>
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<li>The clang/gcc -momit-leaf-frame-pointer argument is now supported.</li>
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<li>The clang/gcc -ffunction-sections and -fdata-sections arguments are now
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supported on ELF targets (like GCC).</li>
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<li>The MachineCSE pass is now tuned and on by default. It eliminates common
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subexpressions that are exposed when lowering to machine instructions.</li>
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<li>The "local" register allocator was replaced by a new "fast" register
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allocator. This new allocator (which is often used at -O0) is substantially
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faster and produces better code than the old local register allocator.</li>
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<li>A new LLC "-regalloc=default" option is available, which automatically
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chooses a register allocator based on the -O optimization level.</li>
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<li>The common code generator code was modified to promote illegal argument and
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return value vectors to wider ones when possible instead of scalarizing
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them. For example, <3 x float> will now pass in one SSE register
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instead of 3 on X86. This generates substantially better code since the
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rest of the code generator was already expecting this.</li>
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<li>The code generator uses a new "COPY" machine instruction. This speeds up
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the code generator and eliminates the need for targets to implement the
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isMoveInstr hook. Also, the copyRegToReg hook was renamed to copyPhysReg
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and simplified.</li>
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<li>The code generator now has a "LocalStackSlotPass", which optimizes stack
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slot access for targets (like ARM) that have limited stack displacement
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addressing.</li>
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<li>A new "PeepholeOptimizer" is available, which eliminates sign and zero
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extends, and optimizes away compare instructions when the condition result
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is available from a previous instruction.</li>
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<li>Atomic operations now get legalized into simpler atomic operations if not
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natively supported, easy the implementation burden on targets.</li>
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<li>The bottom-up pre-allocation scheduler is now register pressure aware,
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allowing it to avoid overscheduling in high pressure situations while still
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aggressively scheduling when registers are available.</li>
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<li>A new instruction-level-parallelism pre-allocation scheduler is available,
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which is also register pressure aware. This scheduler has shown substantial
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wins on X86-64 and is on by default.</li>
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<li>The tblgen type inference algorithm was rewritten to be more consistent and
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diagnose more target bugs. If you have an out-of-tree backend, you may
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find that it finds bugs in your target description. This support also
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allows limited support for writing patterns for instructions that return
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multiple results (e.g. a virtual register and a flag result). The
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'parallel' modifier in tblgen was removed, you should use the new support
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for multiple results instead.</li>
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<li>A new (experimental) "-rendermf" pass is available which renders a
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MachineFunction into HTML, showing live ranges and other useful
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details.</li>
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MachineCSE tuned and on by default.
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<!--New SubRegIndex tblgen class for targets -> jakob -->
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<!-- SplitKit -->
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Rewrote tblgen's type inference for backends to be more consistent and
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diagnose more target bugs. This also allows limited support for writing
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patterns for instructions that return multiple results, e.g. a virtual
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register and a flag result. Stuff that used 'parallel' before should use
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this.
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New -regalloc=fast, =local got removed
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New -regalloc=default option that chooses a register allocator based on the -O optimization level.
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New SubRegIndex tblgen class for targets -> jakob
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Bottom up fast isel. Simple Load reuse. No more machinedce.
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IR ABI: <3 x float> is passed as <4 x float> instead of 3 floats.
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New COPY instruction. copyRegToReg -> copyPhysReg, isMoveInstr is gone.
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RenderMachineFunction: -rendermf
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SplitKit?
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Evan: Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
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Evan: Add an ILP scheduler. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%.
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New OptimizeExts+OptimizeCmps -> PeepholeOptimizer pass
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New LocalStackSlotAllocation.cpp pass (jimg)
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Atomics now get legalized when not natively supported (jim g)
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-ffunction-sections and -fdata-sections are supported on ELF targets.
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-momit-leaf-frame-pointer now supported.
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<li>The -fast-isel instruction selection path (used at -O0 on X86) was rewritten
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to work bottom-up on basic blocks instead of top down. This makes it
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slightly faster (because the MachineDCE pass is not needed any longer) and
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allows it to generate better code in some cases.</li>
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</ul>
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</div>
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@ -860,24 +866,6 @@ it run faster:</p>
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</ul>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="newapis">New Useful APIs</a>
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</div>
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<div class="doc_text">
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<p>This release includes a number of new APIs that are used internally, which
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may also be useful for external clients.
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</p>
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<ul>
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<li></li>
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</ul>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="otherimprovements">Other Improvements and New Features</a>
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