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AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC.

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I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
2013-12-11 14:31:04 +00:00
parent e54c1060a6
commit 3bf51cf302
11 changed files with 174 additions and 171 deletions
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19
test/CodeGen/X86/avx512-vbroadcast.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
;CHECK-LABEL: _inreg16xi32:
;CHECK: vpbroadcastd {{.*}}, %zmm
@@ -19,7 +19,7 @@ define <8 x i64> @_inreg8xi64(i64 %a) {
}
;CHECK-LABEL: _inreg16xfloat:
;CHECK: vbroadcastssz {{.*}}, %zmm
;CHECK: vbroadcastss {{.*}}, %zmm
;CHECK: ret
define <16 x float> @_inreg16xfloat(float %a) {
%b = insertelement <16 x float> undef, float %a, i32 0
@@ -28,7 +28,7 @@ define <16 x float> @_inreg16xfloat(float %a) {
}
;CHECK-LABEL: _inreg8xdouble:
;CHECK: vbroadcastsdz {{.*}}, %zmm
;CHECK: vbroadcastsd {{.*}}, %zmm
;CHECK: ret
define <8 x double> @_inreg8xdouble(double %a) {
%b = insertelement <8 x double> undef, double %a, i32 0
@@ -45,9 +45,20 @@ define <16 x i32> @_xmm16xi32(<16 x i32> %a) {
}
;CHECK-LABEL: _xmm16xfloat
;CHECK: vbroadcastssz
;CHECK: vbroadcastss {{.*}}## encoding: [0x62
;CHECK: ret
define <16 x float> @_xmm16xfloat(<16 x float> %a) {
%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> zeroinitializer
ret <16 x float> %b
}
define <16 x i32> @test_vbroadcast() {
; CHECK: vpbroadcastd
entry:
%0 = sext <16 x i1> zeroinitializer to <16 x i32>
%1 = fcmp uno <16 x float> undef, zeroinitializer
%2 = sext <16 x i1> %1 to <16 x i32>
%3 = select <16 x i1> %1, <16 x i32> %0, <16 x i32> %2
ret <16 x i32> %3
}