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Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This

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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stuart Hastings
2010-06-17 22:43:56 +00:00
parent c22c0f37b4
commit 3bf9125933
34 changed files with 137 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@@ -110,9 +110,8 @@ static bool isAlphaIntCondCode(unsigned Opcode) {
unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
// FIXME this should probably have a DebugLoc argument
DebugLoc dl;
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const {
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
"Alpha branch conditions have two components!");
@@ -120,25 +119,25 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
else // Conditional branch
if (isAlphaIntCondCode(Cond[0].getImm()))
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return 1;
}
// Two-way Conditional Branch.
if (isAlphaIntCondCode(Cond[0].getImm()))
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
return 2;
}

5
lib/Target/Alpha/AlphaInstrInfo.h
View File

@@ -42,8 +42,9 @@ public:
int &FrameIndex) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,