mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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c22c0f37b4
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3bf9125933
@ -286,7 +286,7 @@ protected:
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/// FastEmitBranch - Emit an unconditional branch to the given block,
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/// unless it is the immediate (fall-through) successor, and update
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/// the CFG.
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void FastEmitBranch(MachineBasicBlock *MBB);
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void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
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unsigned UpdateValueMap(const Value* I, unsigned Reg);
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@ -316,7 +316,8 @@ public:
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/// merging needs to be disabled.
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
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return 0;
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}
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@ -373,7 +373,8 @@ void BranchFolder::ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
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// If OldBB isn't immediately before OldBB, insert a branch to it.
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if (++MachineFunction::iterator(OldBB) != MachineFunction::iterator(NewDest))
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TII->InsertBranch(*OldBB, NewDest, 0, SmallVector<MachineOperand, 0>());
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TII->InsertBranch(*OldBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
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OldInst->getDebugLoc());
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OldBB->addSuccessor(NewDest);
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++NumTailMerge;
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}
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@ -443,18 +444,20 @@ static void FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB,
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MachineFunction::iterator I = llvm::next(MachineFunction::iterator(CurMBB));
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MachineBasicBlock *TBB = 0, *FBB = 0;
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SmallVector<MachineOperand, 4> Cond;
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DebugLoc dl; // FIXME: this is nowhere
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if (I != MF->end() &&
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!TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) {
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MachineBasicBlock *NextBB = I;
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if (TBB == NextBB && !Cond.empty() && !FBB) {
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if (!TII->ReverseBranchCondition(Cond)) {
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TII->RemoveBranch(*CurMBB);
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TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond);
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TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond, dl);
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return;
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}
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}
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}
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TII->InsertBranch(*CurMBB, SuccBB, NULL, SmallVector<MachineOperand, 0>());
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TII->InsertBranch(*CurMBB, SuccBB, NULL,
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SmallVector<MachineOperand, 0>(), dl);
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}
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bool
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@ -874,10 +877,11 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
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}
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// Remove the unconditional branch at the end, if any.
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if (TBB && (Cond.empty() || FBB)) {
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DebugLoc dl; // FIXME: this is nowhere
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TII->RemoveBranch(*PBB);
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if (!Cond.empty())
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// reinsert conditional branch only, for now
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TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond);
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TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond, dl);
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}
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MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P));
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}
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@ -976,6 +980,7 @@ static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
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bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
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bool MadeChange = false;
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MachineFunction &MF = *MBB->getParent();
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DebugLoc dl; // FIXME: this is nowhere
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ReoptimizeBlock:
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MachineFunction::iterator FallThrough = MBB;
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@ -1027,7 +1032,7 @@ ReoptimizeBlock:
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TII->RemoveBranch(PrevBB);
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PriorCond.clear();
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if (PriorTBB != MBB)
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TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond);
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TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond, dl);
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MadeChange = true;
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++NumBranchOpts;
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goto ReoptimizeBlock;
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@ -1066,7 +1071,7 @@ ReoptimizeBlock:
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// the condition is false, remove the uncond second branch.
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if (PriorFBB == MBB) {
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TII->RemoveBranch(PrevBB);
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TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond);
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TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond, dl);
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MadeChange = true;
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++NumBranchOpts;
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goto ReoptimizeBlock;
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@ -1079,7 +1084,7 @@ ReoptimizeBlock:
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SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
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if (!TII->ReverseBranchCondition(NewPriorCond)) {
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TII->RemoveBranch(PrevBB);
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TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond);
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TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond, dl);
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MadeChange = true;
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++NumBranchOpts;
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goto ReoptimizeBlock;
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@ -1116,7 +1121,7 @@ ReoptimizeBlock:
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<< "To make fallthrough to: " << *PriorTBB << "\n");
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TII->RemoveBranch(PrevBB);
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TII->InsertBranch(PrevBB, MBB, 0, NewPriorCond);
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TII->InsertBranch(PrevBB, MBB, 0, NewPriorCond, dl);
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// Move this block to the end of the function.
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MBB->moveAfter(--MF.end());
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@ -1145,7 +1150,7 @@ ReoptimizeBlock:
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SmallVector<MachineOperand, 4> NewCond(CurCond);
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if (!TII->ReverseBranchCondition(NewCond)) {
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TII->RemoveBranch(*MBB);
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TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond);
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TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond, dl);
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MadeChange = true;
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++NumBranchOpts;
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goto ReoptimizeBlock;
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@ -1200,7 +1205,7 @@ ReoptimizeBlock:
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PriorFBB = MBB;
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}
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TII->RemoveBranch(PrevBB);
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TII->InsertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond);
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TII->InsertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, dl);
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}
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// Iterate through all the predecessors, revectoring each in-turn.
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@ -1226,7 +1231,7 @@ ReoptimizeBlock:
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if (!NewCurUnAnalyzable && NewCurTBB && NewCurTBB == NewCurFBB) {
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TII->RemoveBranch(*PMBB);
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NewCurCond.clear();
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TII->InsertBranch(*PMBB, NewCurTBB, 0, NewCurCond);
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TII->InsertBranch(*PMBB, NewCurTBB, 0, NewCurCond, dl);
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MadeChange = true;
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++NumBranchOpts;
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PMBB->CorrectExtraCFGEdges(NewCurTBB, 0, false);
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@ -1246,7 +1251,7 @@ ReoptimizeBlock:
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}
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// Add the branch back if the block is more than just an uncond branch.
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TII->InsertBranch(*MBB, CurTBB, 0, CurCond);
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TII->InsertBranch(*MBB, CurTBB, 0, CurCond, dl);
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}
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}
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@ -1286,7 +1291,7 @@ ReoptimizeBlock:
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if (CurFallsThru) {
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MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
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CurCond.clear();
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TII->InsertBranch(*MBB, NextBB, 0, CurCond);
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TII->InsertBranch(*MBB, NextBB, 0, CurCond, dl);
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}
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MBB->moveAfter(PredBB);
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MadeChange = true;
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@ -395,9 +395,10 @@ static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
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/// ReverseBranchCondition - Reverse the condition of the end of the block
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/// branch. Swap block's 'true' and 'false' successors.
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bool IfConverter::ReverseBranchCondition(BBInfo &BBI) {
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DebugLoc dl; // FIXME: this is nowhere
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if (!TII->ReverseBranchCondition(BBI.BrCond)) {
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TII->RemoveBranch(*BBI.BB);
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TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond);
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TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
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std::swap(BBI.TrueBB, BBI.FalseBB);
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return true;
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}
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@ -862,8 +863,9 @@ void IfConverter::InvalidatePreds(MachineBasicBlock *BB) {
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///
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static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
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const TargetInstrInfo *TII) {
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DebugLoc dl; // FIXME: this is nowhere
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SmallVector<MachineOperand, 0> NoCond;
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TII->InsertBranch(*BB, ToBB, NULL, NoCond);
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TII->InsertBranch(*BB, ToBB, NULL, NoCond, dl);
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}
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/// RemoveExtraEdges - Remove true / false edges if either / both are no longer
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@ -1014,6 +1016,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
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BBInfo *CvtBBI = &TrueBBI;
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BBInfo *NextBBI = &FalseBBI;
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DebugLoc dl; // FIXME: this is nowhere
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SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
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if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
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@ -1078,7 +1081,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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CvtBBI->BrCond.end());
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if (TII->ReverseBranchCondition(RevCond))
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assert(false && "Unable to reverse branch condition!");
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TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond);
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TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond, dl);
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BBI.BB->addSuccessor(CvtBBI->FalseBB);
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}
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@ -245,6 +245,7 @@ void MachineBasicBlock::updateTerminator() {
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MachineBasicBlock *TBB = 0, *FBB = 0;
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SmallVector<MachineOperand, 4> Cond;
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DebugLoc dl; // FIXME: this is nowhere
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bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
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(void) B;
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assert(!B && "UpdateTerminators requires analyzable predecessors!");
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@ -259,7 +260,7 @@ void MachineBasicBlock::updateTerminator() {
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// its layout successor, insert a branch.
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TBB = *succ_begin();
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if (!isLayoutSuccessor(TBB))
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TII->InsertBranch(*this, TBB, 0, Cond);
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TII->InsertBranch(*this, TBB, 0, Cond, dl);
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}
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} else {
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if (FBB) {
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@ -270,10 +271,10 @@ void MachineBasicBlock::updateTerminator() {
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if (TII->ReverseBranchCondition(Cond))
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return;
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TII->RemoveBranch(*this);
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TII->InsertBranch(*this, FBB, 0, Cond);
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TII->InsertBranch(*this, FBB, 0, Cond, dl);
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} else if (isLayoutSuccessor(FBB)) {
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TII->RemoveBranch(*this);
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TII->InsertBranch(*this, TBB, 0, Cond);
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TII->InsertBranch(*this, TBB, 0, Cond, dl);
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}
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} else {
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// The block has a fallthrough conditional branch.
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@ -284,14 +285,14 @@ void MachineBasicBlock::updateTerminator() {
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if (TII->ReverseBranchCondition(Cond)) {
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// We can't reverse the condition, add an unconditional branch.
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Cond.clear();
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TII->InsertBranch(*this, MBBA, 0, Cond);
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TII->InsertBranch(*this, MBBA, 0, Cond, dl);
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return;
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}
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TII->RemoveBranch(*this);
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TII->InsertBranch(*this, MBBA, 0, Cond);
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TII->InsertBranch(*this, MBBA, 0, Cond, dl);
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} else if (!isLayoutSuccessor(MBBA)) {
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TII->RemoveBranch(*this);
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TII->InsertBranch(*this, TBB, MBBA, Cond);
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TII->InsertBranch(*this, TBB, MBBA, Cond, dl);
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}
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}
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}
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@ -402,6 +402,7 @@ MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
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assert(A && B && "Missing MBB end point");
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MachineFunction *MF = A->getParent();
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DebugLoc dl; // FIXME: this is nowhere
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// We may need to update A's terminator, but we can't do that if AnalyzeBranch
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// fails. If A uses a jump table, we won't touch it.
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@ -427,7 +428,7 @@ MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
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NMBB->addSuccessor(B);
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if (!NMBB->isLayoutSuccessor(B)) {
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Cond.clear();
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MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
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MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond, dl);
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}
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// Fix PHI nodes in B so they refer to NMBB instead of A
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@ -655,12 +655,12 @@ FastISel::SelectInstruction(const Instruction *I) {
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/// unless it is the immediate (fall-through) successor, and update
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/// the CFG.
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void
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FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
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FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
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if (MBB->isLayoutSuccessor(MSucc)) {
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// The unconditional fall-through case, which needs no instructions.
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} else {
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// The unconditional branch case.
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TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
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TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>(), DL);
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}
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MBB->addSuccessor(MSucc);
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}
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@ -763,7 +763,7 @@ FastISel::SelectOperator(const User *I, unsigned Opcode) {
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if (BI->isUnconditional()) {
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const BasicBlock *LLVMSucc = BI->getSuccessor(0);
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MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
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FastEmitBranch(MSucc);
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FastEmitBranch(MSucc, BI->getDebugLoc());
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return true;
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}
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@ -348,10 +348,8 @@ unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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unsigned
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ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc argument
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DebugLoc dl;
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
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int BOpc = !AFI->isThumbFunction()
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? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
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@ -365,17 +363,17 @@ ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch?
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BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
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BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
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else
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BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
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BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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return 1;
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}
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// Two-way conditional branch.
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BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
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BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
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BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
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return 2;
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}
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@ -225,7 +225,8 @@ public:
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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@ -110,9 +110,8 @@ static bool isAlphaIntCondCode(unsigned Opcode) {
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unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc argument
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DebugLoc dl;
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"Alpha branch conditions have two components!");
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@ -120,25 +119,25 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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// One-way branch.
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
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BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
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else // Conditional branch
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if (isAlphaIntCondCode(Cond[0].getImm()))
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BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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else
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BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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return 1;
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}
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// Two-way Conditional Branch.
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if (isAlphaIntCondCode(Cond[0].getImm()))
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BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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else
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BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
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BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
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return 2;
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}
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||||
|
@ -43,7 +43,8 @@ public:
|
||||
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
@ -104,10 +104,8 @@ unsigned BlackfinInstrInfo::
|
||||
InsertBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc operand
|
||||
DebugLoc DL;
|
||||
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
|
@ -44,7 +44,8 @@ namespace llvm {
|
||||
InsertBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
|
@ -554,9 +554,8 @@ SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
unsigned
|
||||
SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc argument
|
||||
DebugLoc dl;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
||||
@ -566,14 +565,14 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (FBB == 0) {
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch
|
||||
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
|
||||
MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR));
|
||||
MIB.addMBB(TBB);
|
||||
|
||||
DEBUG(errs() << "Inserted one-way uncond branch: ");
|
||||
DEBUG((*MIB).dump());
|
||||
} else {
|
||||
// Conditional branch
|
||||
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
|
||||
MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
|
||||
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
|
||||
DEBUG(errs() << "Inserted one-way cond branch: ");
|
||||
@ -581,8 +580,8 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
}
|
||||
return 1;
|
||||
} else {
|
||||
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
|
||||
MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
|
||||
MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
|
||||
MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
|
||||
|
||||
// Two-way Conditional Branch.
|
||||
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
|
@ -95,7 +95,8 @@ namespace llvm {
|
||||
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -185,10 +185,11 @@ foldMemoryOperandImpl(MachineFunction &MF,
|
||||
unsigned MBlazeInstrInfo::
|
||||
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Can only insert uncond branches so far.
|
||||
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
|
||||
BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(MBlaze::BRI)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
@ -198,7 +198,8 @@ public:
|
||||
/// Branch Analysis
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
@ -330,10 +330,8 @@ bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
unsigned
|
||||
MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc operand
|
||||
DebugLoc DL;
|
||||
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
|
@ -93,7 +93,8 @@ public:
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
|
||||
};
|
||||
|
||||
|
@ -520,9 +520,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
unsigned MipsInstrInfo::
|
||||
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc argument
|
||||
DebugLoc dl;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
|
||||
@ -531,18 +530,18 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (FBB == 0) { // One way branch.
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
|
||||
} else {
|
||||
// Conditional branch.
|
||||
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
|
||||
if (TID.getNumOperands() == 3)
|
||||
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
|
||||
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
|
||||
.addReg(Cond[2].getReg())
|
||||
.addMBB(TBB);
|
||||
else
|
||||
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
|
||||
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
|
||||
.addMBB(TBB);
|
||||
|
||||
}
|
||||
@ -554,12 +553,12 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
|
||||
if (TID.getNumOperands() == 3)
|
||||
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
|
||||
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
|
||||
.addMBB(TBB);
|
||||
else
|
||||
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
|
||||
BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
|
||||
return 2;
|
||||
}
|
||||
|
||||
|
@ -204,7 +204,8 @@ public:
|
||||
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
@ -196,15 +196,15 @@ bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
|
||||
unsigned PIC16InstrInfo::
|
||||
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
|
||||
if (FBB == 0) { // One way branch.
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
DebugLoc dl;
|
||||
BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(PIC16::br_uncond)).addMBB(TBB);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
@ -70,7 +70,8 @@ public:
|
||||
virtual
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
|
@ -316,9 +316,8 @@ unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
unsigned
|
||||
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc argument
|
||||
DebugLoc dl;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
||||
@ -327,17 +326,17 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
// One-way branch.
|
||||
if (FBB == 0) {
|
||||
if (Cond.empty()) // Unconditional branch
|
||||
BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
|
||||
else // Conditional branch
|
||||
BuildMI(&MBB, dl, get(PPC::BCC))
|
||||
BuildMI(&MBB, DL, get(PPC::BCC))
|
||||
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Two-way Conditional Branch.
|
||||
BuildMI(&MBB, dl, get(PPC::BCC))
|
||||
BuildMI(&MBB, DL, get(PPC::BCC))
|
||||
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
|
||||
return 2;
|
||||
}
|
||||
|
||||
|
@ -109,7 +109,8 @@ public:
|
||||
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
@ -109,12 +109,11 @@ unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
||||
unsigned
|
||||
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond)const{
|
||||
// FIXME this should probably take a DebugLoc argument
|
||||
DebugLoc dl;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL)const{
|
||||
// Can only insert uncond branches so far.
|
||||
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
|
||||
BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
@ -68,7 +68,8 @@ public:
|
||||
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
|
@ -521,9 +521,8 @@ unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
unsigned
|
||||
SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME: this should probably have a DebugLoc operand
|
||||
DebugLoc DL;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
|
@ -102,7 +102,8 @@ public:
|
||||
bool AllowModify) const;
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
|
||||
SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
|
||||
|
@ -891,7 +891,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
|
||||
BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
|
||||
}
|
||||
|
||||
FastEmitBranch(FalseMBB);
|
||||
FastEmitBranch(FalseMBB, DL);
|
||||
MBB->addSuccessor(TrueMBB);
|
||||
return true;
|
||||
}
|
||||
@ -946,7 +946,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
|
||||
BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
|
||||
X86::JO_4 : X86::JB_4))
|
||||
.addMBB(TrueMBB);
|
||||
FastEmitBranch(FalseMBB);
|
||||
FastEmitBranch(FalseMBB, DL);
|
||||
MBB->addSuccessor(TrueMBB);
|
||||
return true;
|
||||
}
|
||||
@ -961,7 +961,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
|
||||
|
||||
BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
|
||||
BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
|
||||
FastEmitBranch(FalseMBB);
|
||||
FastEmitBranch(FalseMBB, DL);
|
||||
MBB->addSuccessor(TrueMBB);
|
||||
return true;
|
||||
}
|
||||
|
@ -1839,9 +1839,8 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
unsigned
|
||||
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc operand
|
||||
DebugLoc dl;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
@ -1850,7 +1849,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
assert(!FBB && "Unconditional branch with multiple successors!");
|
||||
BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -1860,27 +1859,27 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
switch (CC) {
|
||||
case X86::COND_NP_OR_E:
|
||||
// Synthesize NP_OR_E with two branches.
|
||||
BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
|
||||
++Count;
|
||||
BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
|
||||
++Count;
|
||||
break;
|
||||
case X86::COND_NE_OR_P:
|
||||
// Synthesize NE_OR_P with two branches.
|
||||
BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
|
||||
++Count;
|
||||
BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
|
||||
++Count;
|
||||
break;
|
||||
default: {
|
||||
unsigned Opc = GetCondBranchFromCond(CC);
|
||||
BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
|
||||
++Count;
|
||||
}
|
||||
}
|
||||
if (FBB) {
|
||||
// Two-way Conditional branch. Insert the second branch.
|
||||
BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
|
||||
++Count;
|
||||
}
|
||||
return Count;
|
||||
|
@ -612,7 +612,8 @@ public:
|
||||
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
@ -299,9 +299,8 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
unsigned
|
||||
XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond)const{
|
||||
// FIXME there should probably be a DebugLoc argument here
|
||||
DebugLoc dl;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL)const{
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
||||
@ -310,11 +309,11 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
if (FBB == 0) { // One way branch.
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch
|
||||
BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
|
||||
} else {
|
||||
// Conditional branch.
|
||||
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
|
||||
BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
|
||||
BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
|
||||
.addMBB(TBB);
|
||||
}
|
||||
return 1;
|
||||
@ -323,9 +322,9 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
// Two-way Conditional branch.
|
||||
assert(Cond.size() == 2 && "Unexpected number of components!");
|
||||
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
|
||||
BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
|
||||
BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
|
||||
.addMBB(TBB);
|
||||
BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
|
||||
return 2;
|
||||
}
|
||||
|
||||
|
@ -59,7 +59,8 @@ public:
|
||||
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const;
|
||||
|
||||
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user