diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index cf23f2a4409..f6891da8e73 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -51,6 +51,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
 
+  setOperationAction(ISD::SETCC, MVT::i32, Expand);
+  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+
   setSchedulingPreference(SchedulingForRegPressure);
   computeRegisterProperties();
 }
@@ -64,7 +67,11 @@ namespace llvm {
       CALL,
 
       /// Return with a flag operand.
-      RET_FLAG
+      RET_FLAG,
+
+      CMP,
+
+      SELECT
     };
   }
 }
@@ -74,6 +81,8 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   default: return 0;
   case ARMISD::CALL:          return "ARMISD::CALL";
   case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
+  case ARMISD::SELECT:        return "ARMISD::SELECT";
+  case ARMISD::CMP:           return "ARMISD::CMP";
   }
 }
 
@@ -290,6 +299,19 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
   return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
 }
 
+static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
+  SDOperand LHS = Op.getOperand(0);
+  SDOperand RHS = Op.getOperand(1);
+  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
+  SDOperand TrueVal = Op.getOperand(2);
+  SDOperand FalseVal = Op.getOperand(3);
+
+  assert(CC == ISD::SETEQ);
+
+  SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
+  return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
+}
+
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default:
@@ -305,6 +327,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return LowerCALL(Op, DAG);
   case ISD::RET:
     return LowerRET(Op, DAG);
+  case ISD::SELECT_CC:
+    return LowerSELECT_CC(Op, DAG);
   }
 }
 
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 55dc747b134..87e368594d1 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -48,6 +48,10 @@ def ARMcall        : SDNode<"ARMISD::CALL", SDT_ARMcall,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 def retflag        : SDNode<"ARMISD::RET_FLAG", SDTRet,
 	                   [SDNPHasChain, SDNPOptInFlag]>;
+def armselect      : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
+
+def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
+def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
 
 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
                             "!ADJCALLSTACKUP $amt",
@@ -96,3 +100,13 @@ def subri   : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
 def andrr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
 		       "and $dst, $a, $b",
 		       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
+
+let isTwoAddress = 1 in {
+  def moveq    : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true),
+	                 "moveq $dst, $true",
+		         [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
+}
+
+def cmp      : InstARM<(ops IntRegs:$a, IntRegs:$b),
+	               "cmp $a, $b",
+		       [(armcmp IntRegs:$a, IntRegs:$b)]>;
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 1ed9292ccb6..bd6664250cd 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -61,6 +61,9 @@ bool ARMTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
   if (!Fast)
     PM.add(createLoopStrengthReducePass());
 
+  if (!Fast)
+    PM.add(createCFGSimplificationPass());
+
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
 
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
new file mode 100644
index 00000000000..71c5ebafe80
--- /dev/null
+++ b/test/CodeGen/ARM/select.ll
@@ -0,0 +1,15 @@
+int %f(int %a) {
+entry:
+	%tmp = seteq int %a, 4		; <bool> [#uses=1]
+	br bool %tmp, label %cond_false, label %cond_true
+
+cond_true:		; preds = %entry
+	br label %return
+
+cond_false:		; preds = %entry
+	br label %return
+
+return:		; preds = %cond_false, %cond_true
+	%retval.0 = phi int [ 2, %cond_true ], [ 3, %cond_false ]		; <int> [#uses=1]
+	ret int %retval.0
+}