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Check in some intermediate code that adds a skeleton for matching vsplt*
instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -82,7 +82,19 @@ namespace llvm {
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/// Return with a flag operand, matched by 'blr'
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/// Return with a flag operand, matched by 'blr'
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RET_FLAG,
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RET_FLAG,
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};
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};
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}
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}
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/// Define some predicates that are used for node matching.
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namespace PPC {
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/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element that is suitable for input to
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/// VSPLTB/VSPLTH/VSPLTW.
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bool isSplatShuffleMask(SDNode *N) { return false; } // FIXME:
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/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
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/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
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unsigned getVSPLTImmediate(SDNode *N) { return 0; } // FIXME:
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}
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class PPCTargetLowering : public TargetLowering {
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class PPCTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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@ -123,6 +123,14 @@ def imm16Shifted : PatLeaf<(imm), [{
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return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
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return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
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}], HI16>;
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}], HI16>;
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// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
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def VSPLT_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N));
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}]>;
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def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N);
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}], VSPLT_get_imm>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PowerPC Flag Definitions.
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// PowerPC Flag Definitions.
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@ -937,6 +945,7 @@ def RLDICR : MDForm_1<30, 1,
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[]>, isPPC64;
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[]>, isPPC64;
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}
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}
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let PPC970_Unit = 5 in { // VALU Operations.
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let PPC970_Unit = 5 in { // VALU Operations.
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// VA-Form instructions. 3-input AltiVec ops.
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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@ -1022,9 +1031,11 @@ def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vsplth $vD, $vB, $UIMM", VecPerm,
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"vsplth $vD, $vB, $UIMM", VecPerm,
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[]>;
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[]>;
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def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltw $vD, $vB, $UIMM", VecPerm,
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//def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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[]>;
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// "vspltw $vD, $vB, $UIMM", VecPerm,
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// [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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// VSPLT_shuffle_mask:$UIMM))]>;
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// VX-Form Pseudo Instructions
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// VX-Form Pseudo Instructions
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@ -1033,6 +1044,7 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
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[]>;
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[]>;
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// DWARF Pseudo Instructions
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// DWARF Pseudo Instructions
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//
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//
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