mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -4810,3 +4810,21 @@ Hexagon_di_di_Intrinsic<"HEXAGON_S2_interleave">;
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//
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def int_hexagon_S2_deinterleave :
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Hexagon_di_di_Intrinsic<"HEXAGON_S2_deinterleave">;
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def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
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def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
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// Mark locked loads as read/write to prevent any accidental reordering.
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def int_hexagon_L2_loadw_locked :
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Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
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[IntrReadWriteArgMem, NoCapture<0>]>;
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def int_hexagon_L4_loadd_locked :
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Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
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[IntrReadWriteArgMem, NoCapture<0>]>;
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def int_hexagon_S2_storew_locked :
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Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
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[llvm_ptr32_ty, llvm_i32_ty], [IntrReadWriteArgMem, NoCapture<0>]>;
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def int_hexagon_S4_stored_locked :
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Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
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[llvm_ptr64_ty, llvm_i64_ty], [IntrReadWriteArgMem, NoCapture<0>]>;
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@@ -224,6 +224,12 @@ def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
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def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
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}
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// Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
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let hasSideEffects = 0 in
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def M2_vrcmpys_s1
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: MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
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"$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
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// Vector reduce complex multiply by scalar with accumulation.
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let Defs = [USR_OVF], hasSideEffects = 0 in
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class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
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@@ -250,11 +256,25 @@ def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
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def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
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}
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// Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
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def M2_vrcmpys_acc_s1
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: MInst <(outs DoubleRegs:$dst),
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(ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
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"$dst += vrcmpys($src1, $src2):<<1:sat", [],
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"$dst2 = $dst">;
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let isCodeGenOnly = 0 in {
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def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
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def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
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}
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// Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
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def M2_vrcmpys_s1rp
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: MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
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"$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
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// S2_cabacdecbin: Cabac decode bin.
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let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23,
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isCodeGenOnly = 0 in
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@@ -808,6 +808,10 @@ def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
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let Inst{4-0} = Rdd;
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}
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def S5_vasrhrnd_goodsyntax
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: SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4Imm:$u4),
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"$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>;
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// Floating point reciprocal square root approximation
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let Uses = [USR], isPredicateLate = 1, isFP = 1,
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hasSideEffects = 0, hasNewValue = 1, opNewValue = 0,
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@@ -1136,7 +1136,6 @@ def : T_R_pat <S2_vzxthw, int_hexagon_S2_vzxthw>;
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def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>;
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def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>;
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// Vector saturate and pack
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def : T_R_pat <S2_svsathb, int_hexagon_S2_svsathb>;
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def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>;
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@@ -1164,6 +1163,9 @@ def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>;
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def : T_R_pat <A2_satub, int_hexagon_A2_satub>;
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def : T_R_pat <A2_satb, int_hexagon_A2_satb>;
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// Vector arithmetic shift right by immediate with truncate and pack.
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def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>;
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def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>;
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def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>;
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def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>;
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@@ -1201,599 +1203,60 @@ def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
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def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
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DEC3_CONST_SIGNED>;
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//
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// ALU 32 types.
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//
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class qi_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_ALU32_sis10<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class qi_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class qi_ALU32_siu8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class qi_ALU32_siu9<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class si_ALU32_qisisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class di_ALU64_di<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "$src")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
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//
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// ALU 64 types.
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//
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class di_ALU64_didi<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
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DoubleRegs:$src2))]>;
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class di_ALU64_qididi<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
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DoubleRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
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[(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
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DoubleRegs:$src3))]>;
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class di_ALU64_didi_sat<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
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DoubleRegs:$src2))]>;
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class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
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DoubleRegs:$src2))]>;
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class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
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DoubleRegs:$src2))]>;
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class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
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DoubleRegs:$src2))]>;
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class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
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DoubleRegs:$src2))]>;
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class qi_ALU64_didi<string opc, Intrinsic IntID>
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: ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
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//
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// SInst classes.
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//
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class qi_SInst_qi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src))]>;
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class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "$src")),
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[(set PredRegs:$dst, (IntID IntRegs:$src))]>;
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class qi_SInst_qiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class di_SInst_di<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
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class di_SInst_di_sat<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src):sat")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
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class si_SInst_di<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src)")),
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[(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
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class si_SInst_di_sat<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src):sat")),
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[(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
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class di_SInst_disi<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
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class di_SInst_didi<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
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class di_SInst_si<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
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!strconcat("$dst = ", !strconcat(opc , "($src1)")),
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[(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
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class si_SInst_diu5<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
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class si_SInst_disi<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
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class si_SInst_si<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src))]>;
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class di_SInst_qi<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "($src)")),
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[(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
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class si_SInst_qi<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "$src")),
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[(set IntRegs:$dst, (IntID IntRegs:$src))]>;
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class si_SInst_qiqi<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_SInst_si<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
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!strconcat("$dst = ", !strconcat(opc , "$src")),
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[(set PredRegs:$dst, (IntID IntRegs:$src))]>;
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class di_SInst_didiqi<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
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IntRegs:$src3))]>;
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class di_SInst_didiu3<string opc, Intrinsic IntID>
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: SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
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u3Imm:$src3),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
|
||||
imm:$src3))]>;
|
||||
|
||||
|
||||
//
|
||||
// MInst classes.
|
||||
//
|
||||
|
||||
class di_MInst_disisi_acc<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_nac<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst -= ", !strconcat(opc ,
|
||||
"($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc ,
|
||||
"($src1, $src2*):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst -= ", !strconcat(opc ,
|
||||
"($src1, $src2*):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_didi<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))]>;
|
||||
|
||||
class di_MInst_didi_conj<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))]>;
|
||||
|
||||
class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2*):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2):<<1:rnd:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))]>;
|
||||
|
||||
class di_MInst_didi_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))]>;
|
||||
|
||||
class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2):rnd:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))]>;
|
||||
|
||||
class si_SInst_didi_sat<string opc, Intrinsic IntID>
|
||||
: SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
|
||||
[(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
|
||||
|
||||
class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2):<<1:rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2):<<1:rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2*):rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2*):<<1:rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2):rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_sisi<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_sisi_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))]>;
|
||||
|
||||
class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc ,
|
||||
"($src1, $src2):<<1:rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
|
||||
|
||||
class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
|
||||
|
||||
class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
|
||||
DoubleRegs:$src2),
|
||||
!strconcat("$dst += ",
|
||||
!strconcat(opc , "($src1, $src2):rnd:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2),
|
||||
!strconcat("$dst += ",
|
||||
!strconcat(opc , "($src1, $src2):<<1")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
|
||||
class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2),
|
||||
!strconcat("$dst += ",
|
||||
!strconcat(opc , "($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
|
||||
DoubleRegs:$src2),
|
||||
!strconcat("$dst += ",
|
||||
!strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_dididi_acc<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
|
||||
DoubleRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
|
||||
DoubleRegs:$src2),
|
||||
!strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst += ",
|
||||
!strconcat(opc , "($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
|
||||
: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
!strconcat("$dst += ",
|
||||
!strconcat(opc , "($src1, $src2):<<1:sat")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
|
||||
DoubleRegs:$src1,
|
||||
IntRegs:$src2))],
|
||||
"$dst2 = $dst">;
|
||||
|
||||
class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ",
|
||||
!strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
|
||||
[(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class si_MInst_didi<string opc, Intrinsic IntID>
|
||||
: MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
|
||||
|
||||
//
|
||||
// LDInst classes.
|
||||
//
|
||||
let mayLoad = 1, hasSideEffects = 0 in
|
||||
class di_LDInstPI_diu4<string opc, Intrinsic IntID>
|
||||
: LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
|
||||
"$dst2 = memd($src1++#$offset:circ($src3))",
|
||||
[],
|
||||
"$src1 = $dst">;
|
||||
|
||||
/********************************************************************
|
||||
* STYPE/VH *
|
||||
*********************************************************************/
|
||||
|
||||
// STYPE / VH / Vector absolute value halfwords.
|
||||
// Rdd64=vabsh(Rss64)
|
||||
def HEXAGON_A2_vabsh:
|
||||
di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
|
||||
def HEXAGON_A2_vabshsat:
|
||||
di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
|
||||
// Vector absolute value halfwords with and without saturation
|
||||
// Rdd64=vabsh(Rss64)[:sat]
|
||||
def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>;
|
||||
def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>;
|
||||
|
||||
// STYPE / VH / Vector shift halfwords by immediate.
|
||||
// Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
|
||||
def HEXAGON_S2_asl_i_vh:
|
||||
di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
|
||||
def HEXAGON_S2_asr_i_vh:
|
||||
di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
|
||||
def HEXAGON_S2_lsr_i_vh:
|
||||
di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
|
||||
|
||||
// STYPE / VH / Vector shift halfwords by register.
|
||||
// Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
|
||||
def HEXAGON_S2_asl_r_vh:
|
||||
di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
|
||||
def HEXAGON_S2_asr_r_vh:
|
||||
di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
|
||||
def HEXAGON_S2_lsl_r_vh:
|
||||
di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
|
||||
def HEXAGON_S2_lsr_r_vh:
|
||||
di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
|
||||
// Vector shift halfwords by immediate
|
||||
// Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4)
|
||||
def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>;
|
||||
def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>;
|
||||
def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>;
|
||||
|
||||
// Vector shift halfwords by register
|
||||
// Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32)
|
||||
def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>;
|
||||
def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>;
|
||||
def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>;
|
||||
def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>;
|
||||
|
||||
/********************************************************************
|
||||
* STYPE/VW *
|
||||
*********************************************************************/
|
||||
|
||||
// STYPE / VW / Vector absolute value words.
|
||||
def HEXAGON_A2_vabsw:
|
||||
di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
|
||||
def HEXAGON_A2_vabswsat:
|
||||
di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
|
||||
// Vector absolute value words with and without saturation
|
||||
def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>;
|
||||
def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>;
|
||||
|
||||
// STYPE / VW / Vector shift words by immediate.
|
||||
// Rdd64=v[asl/vsl]w(Rss64,Rt32)
|
||||
def HEXAGON_S2_asl_i_vw:
|
||||
di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
|
||||
def HEXAGON_S2_asr_i_vw:
|
||||
di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
|
||||
def HEXAGON_S2_lsr_i_vw:
|
||||
di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
|
||||
// Vector shift words by immediate.
|
||||
// Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5)
|
||||
def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>;
|
||||
def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>;
|
||||
def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>;
|
||||
|
||||
// STYPE / VW / Vector shift words by register.
|
||||
// Rdd64=v[asl/vsl]w(Rss64,Rt32)
|
||||
def HEXAGON_S2_asl_r_vw:
|
||||
di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
|
||||
def HEXAGON_S2_asr_r_vw:
|
||||
di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
|
||||
def HEXAGON_S2_lsl_r_vw:
|
||||
di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
|
||||
def HEXAGON_S2_lsr_r_vw:
|
||||
di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
|
||||
// Vector shift words by register.
|
||||
// Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32)
|
||||
def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>;
|
||||
def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>;
|
||||
def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>;
|
||||
def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>;
|
||||
|
||||
// STYPE / VW / Vector shift words with truncate and pack.
|
||||
def HEXAGON_S2_asr_r_svw_trun:
|
||||
si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
|
||||
def HEXAGON_S2_asr_i_svw_trun:
|
||||
si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
|
||||
// Vector shift words with truncate and pack
|
||||
|
||||
// LD / Circular loads.
|
||||
def HEXAGON_circ_ldd:
|
||||
di_LDInstPI_diu4 <"circ_ldd", int_hexagon_circ_ldd>;
|
||||
def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>;
|
||||
|
||||
def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>;
|
||||
def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>;
|
||||
|
||||
def: Pat<(i32 (int_hexagon_S2_storew_locked (I32:$Rs), (I32:$Rt))),
|
||||
(i32 (C2_tfrpr (S2_storew_locked (I32:$Rs), (I32:$Rt))))>;
|
||||
def: Pat<(i32 (int_hexagon_S4_stored_locked (I32:$Rs), (I64:$Rt))),
|
||||
(i32 (C2_tfrpr (S4_stored_locked (I32:$Rs), (I64:$Rt))))>;
|
||||
|
||||
include "HexagonIntrinsicsV3.td"
|
||||
include "HexagonIntrinsicsV4.td"
|
||||
|
@@ -11,26 +11,13 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Vector reduce complex multiply real or imaginary
|
||||
def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
|
||||
def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
|
||||
def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
|
||||
|
||||
|
||||
|
||||
// MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
|
||||
def Hexagon_M2_vrcmpys_s1:
|
||||
di_MInst_disi_s1_sat <"vrcmpys", int_hexagon_M2_vrcmpys_s1>;
|
||||
def Hexagon_M2_vrcmpys_acc_s1:
|
||||
di_MInst_didisi_acc_s1_sat <"vrcmpys", int_hexagon_M2_vrcmpys_acc_s1>;
|
||||
def Hexagon_M2_vrcmpys_s1rp:
|
||||
si_MInst_disi_s1_rnd_sat <"vrcmpys", int_hexagon_M2_vrcmpys_s1rp>;
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* MTYPE/VB *
|
||||
*********************************************************************/
|
||||
|
||||
// MTYPE / VB / Vector reduce add unsigned bytes.
|
||||
def Hexagon_M2_vradduh:
|
||||
si_MInst_didi <"vradduh", int_hexagon_M2_vradduh>;
|
||||
|
||||
// Vector reduce add unsigned halfwords
|
||||
def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
|
||||
|
||||
def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
|
||||
def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
|
||||
|
@@ -1,4 +1,4 @@
|
||||
//===- HexagonIntrinsicsV5.td - V4 Instruction intrinsics --*- tablegen -*-===//
|
||||
//===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@@ -7,6 +7,32 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//Rdd[+]=vrmpybsu(Rss,Rtt)
|
||||
//Rdd[+]=vrmpybuu(Rss,Rtt)
|
||||
let Predicates = [HasV5T] in {
|
||||
def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
|
||||
def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
|
||||
|
||||
def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
|
||||
|
||||
def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
|
||||
def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
|
||||
//Rxx+=vdmpybsu(Rss,Rtt):sat
|
||||
def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
|
||||
|
||||
// Vector multiply bytes
|
||||
// Rdd=vmpyb[s]u(Rs,Rt)
|
||||
def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
|
||||
def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
|
||||
|
||||
// Rxx+=vmpyb[s]u(Rs,Rt)
|
||||
def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
|
||||
def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
|
||||
|
||||
// Rd=vaddhub(Rss,Rtt):sat
|
||||
def : T_PP_pat <A5_vaddhubs, int_hexagon_A5_vaddhubs>;
|
||||
}
|
||||
|
||||
def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>;
|
||||
def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>;
|
||||
def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>;
|
||||
@@ -30,6 +56,8 @@ def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax,
|
||||
def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax,
|
||||
int_hexagon_S5_asrhub_rnd_sat_goodsyntax>;
|
||||
|
||||
def : T_PI_pat <S5_vasrhrnd_goodsyntax, int_hexagon_S5_vasrhrnd_goodsyntax>;
|
||||
|
||||
def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>;
|
||||
def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>;
|
||||
def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>;
|
||||
@@ -81,53 +109,3 @@ def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>;
|
||||
def : T_D_pat <F2_conv_df2w_chop, int_hexagon_F2_conv_df2w_chop>;
|
||||
def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>;
|
||||
def : T_D_pat <F2_conv_df2d_chop, int_hexagon_F2_conv_df2d_chop>;
|
||||
|
||||
class qi_ALU64_dfdf<string opc, Intrinsic IntID>
|
||||
: ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
|
||||
|
||||
class qi_ALU64_dfu5<string opc, Intrinsic IntID>
|
||||
: ALU64_ri<(outs PredRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
|
||||
[(set PredRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
|
||||
|
||||
class qi_SInst_sfsf<string opc, Intrinsic IntID>
|
||||
: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
|
||||
[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
|
||||
|
||||
class qi_SInst_sfu5<string opc, Intrinsic IntID>
|
||||
: MInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
|
||||
[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
|
||||
|
||||
class di_MInst_diu4_rnd<string opc, Intrinsic IntID>
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u4Imm:$src2),
|
||||
!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
|
||||
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
|
||||
|
||||
def HEXAGON_M5_vrmpybuu:
|
||||
di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>;
|
||||
def HEXAGON_M5_vrmacbuu:
|
||||
di_MInst_dididi_acc <"vrmpybu", int_hexagon_M5_vrmacbuu>;
|
||||
def HEXAGON_M5_vrmpybsu:
|
||||
di_MInst_didi <"vrmpybsu", int_hexagon_M5_vrmpybsu>;
|
||||
def HEXAGON_M5_vrmacbsu:
|
||||
di_MInst_dididi_acc <"vrmpybsu", int_hexagon_M5_vrmacbsu>;
|
||||
def HEXAGON_M5_vmpybuu:
|
||||
di_MInst_sisi <"vmpybu", int_hexagon_M5_vmpybuu>;
|
||||
def HEXAGON_M5_vmpybsu:
|
||||
di_MInst_sisi <"vmpybsu", int_hexagon_M5_vmpybsu>;
|
||||
def HEXAGON_M5_vmacbuu:
|
||||
di_MInst_disisi_acc <"vmpybu", int_hexagon_M5_vmacbuu>;
|
||||
def HEXAGON_M5_vmacbsu:
|
||||
di_MInst_disisi_acc <"vmpybsu", int_hexagon_M5_vmacbsu>;
|
||||
def HEXAGON_M5_vdmpybsu:
|
||||
di_MInst_didi_sat <"vdmpybsu", int_hexagon_M5_vdmpybsu>;
|
||||
def HEXAGON_M5_vdmacbsu:
|
||||
di_MInst_dididi_acc_sat <"vdmpybsu", int_hexagon_M5_vdmacbsu>;
|
||||
def HEXAGON_A5_vaddhubs:
|
||||
si_SInst_didi_sat <"vaddhub", int_hexagon_A5_vaddhubs>;
|
||||
def HEXAGON_S5_vasrhrnd_goodsyntax:
|
||||
di_MInst_diu4_rnd <"vasrh", int_hexagon_S5_vasrhrnd_goodsyntax>;
|
||||
|
@@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
|
||||
; Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU
|
||||
|
||||
; Absolute value doubleword
|
||||
|
@@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
|
||||
; Hexagon Programmer's Reference Manual 11.10.5 XTYPE/MPY
|
||||
|
||||
; Multiply and use lower result
|
||||
|
@@ -633,3 +633,91 @@ define i32 @S2_asl_r_r_sat(i32 %a, i32 %b) {
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = asl(r0, r1):sat
|
||||
|
||||
; Vector shift halfwords by immediate
|
||||
declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32)
|
||||
define i64 @S2_asr_i_vh(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %a, i32 0)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vasrh(r1:0, #0)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32)
|
||||
define i64 @S2_lsr_i_vh(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %a, i32 0)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vlsrh(r1:0, #0)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32)
|
||||
define i64 @S2_asl_i_vh(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %a, i32 0)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaslh(r1:0, #0)
|
||||
|
||||
; Vector shift halfwords by register
|
||||
declare i64 @llvm.hexagon.S2.asr.r.vh(i64, i32)
|
||||
define i64 @S2_asr_r_vh(i64 %a, i32 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.asr.r.vh(i64 %a, i32 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vasrh(r1:0, r2)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.lsr.r.vh(i64, i32)
|
||||
define i64 @S2_lsr_r_vh(i64 %a, i32 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.lsr.r.vh(i64 %a, i32 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vlsrh(r1:0, r2)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.asl.r.vh(i64, i32)
|
||||
define i64 @S2_asl_r_vh(i64 %a, i32 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.asl.r.vh(i64 %a, i32 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaslh(r1:0, r2)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.lsl.r.vh(i64, i32)
|
||||
define i64 @S2_lsl_r_vh(i64 %a, i32 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.lsl.r.vh(i64 %a, i32 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vlslh(r1:0, r2)
|
||||
|
||||
; Vector shift words by immediate
|
||||
declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32)
|
||||
define i64 @S2_asr_i_vw(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %a, i32 0)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vasrw(r1:0, #0)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32)
|
||||
define i64 @S2_lsr_i_vw(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %a, i32 0)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vlsrw(r1:0, #0)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32)
|
||||
define i64 @S2_asl_i_vw(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %a, i32 0)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaslw(r1:0, #0)
|
||||
|
||||
; Vector shift words by with truncate and pack
|
||||
declare i32 @llvm.hexagon.S2.asr.i.svw.trun(i64, i32)
|
||||
define i32 @S2_asr_i_svw_trun(i64 %a) {
|
||||
%z = call i32 @llvm.hexagon.S2.asr.i.svw.trun(i64 %a, i32 0)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vasrw(r1:0, #0)
|
||||
|
||||
declare i32 @llvm.hexagon.S2.asr.r.svw.trun(i64, i32)
|
||||
define i32 @S2_asr_r_svw_trun(i64 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.S2.asr.r.svw.trun(i64 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vasrw(r1:0, r2)
|
||||
|
Reference in New Issue
Block a user