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ldm / stm instruction encodings.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-09-01 07:48:18 +00:00
parent 5d2c1cf74d
commit 3c2ee4939b
2 changed files with 28 additions and 6 deletions
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28
lib/Target/ARM/ARMInstrFormats.td
View File

@ -577,11 +577,33 @@ class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern>;
class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
asm, "", pattern> {
let Inst{25-27} = 0x4;
}
class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern>;
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{22} = 0; // S bit
let Inst{25-27} = 0x4;
}
class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{22} = 1; // S bit
let Inst{25-27} = 0x4;
}
class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 0; // L bit
let Inst{22} = 0; // S bit
let Inst{25-27} = 0x4;
}
// BR_JT instructions

6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -523,7 +523,7 @@ let isReturn = 1, isTerminator = 1 in
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
let isReturn = 1, isTerminator = 1 in
def LDM_RET : AXI4<0x0, (outs),
def LDM_RET : AXI4ldpc<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
[]>;
@ -725,13 +725,13 @@ def STRB_POST: AI2stbpo<0x1, (outs GPR:$base_wb),
// FIXME: $dst1 should be a def.
let mayLoad = 1 in
def LDM : AXI4<0x0, (outs),
def LDM : AXI4ld<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
[]>;
let mayStore = 1 in
def STM : AXI4<0x0, (outs),
def STM : AXI4st<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
StFrm, "stm${p}${addr:submode} $addr, $src1",
[]>;