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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-17 20:29:31 +00:00
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
depending on the command line option. Now the command line option just sets the subtarget as appropriate. G5 opts will now default to on on G5-enabled nightly testers among other machines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22688 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,7 +33,6 @@ FunctionPass *createPPC64ISelPattern(TargetMachine &TM);
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FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
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FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
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FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
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FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
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extern bool GPOPT;
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extern bool PICEnabled;
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extern bool PICEnabled;
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extern PPCTargetEnum PPCTarget;
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extern PPCTargetEnum PPCTarget;
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} // end namespace llvm;
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} // end namespace llvm;
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@ -19,6 +19,7 @@
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#define DEBUG_TYPE "asmprinter"
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#define DEBUG_TYPE "asmprinter"
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#include "PowerPC.h"
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#include "PowerPC.h"
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#include "PowerPCTargetMachine.h"
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#include "PowerPCTargetMachine.h"
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#include "PowerPCSubtarget.h"
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#include "llvm/Constants.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/Module.h"
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@ -440,7 +441,8 @@ void DarwinAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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}
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}
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bool DarwinAsmPrinter::doInitialization(Module &M) {
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bool DarwinAsmPrinter::doInitialization(Module &M) {
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if (GPOPT) O << "\t.machine ppc970\n";
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if (TM.getSubtarget<PPCSubtarget>().isGigaProcessor())
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O << "\t.machine ppc970\n";
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AsmPrinter::doInitialization(M);
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AsmPrinter::doInitialization(M);
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return false;
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return false;
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}
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}
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@ -96,7 +96,7 @@ namespace {
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setOperationAction(ISD::SREM , MVT::f32, Expand);
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setOperationAction(ISD::SREM , MVT::f32, Expand);
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// If we're enabling GP optimizations, use hardware square root
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// If we're enabling GP optimizations, use hardware square root
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if (!GPOPT) {
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if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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}
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}
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@ -536,6 +536,7 @@ namespace {
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Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
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Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
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Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
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Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
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Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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/// SelectionDAG operations.
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/// SelectionDAG operations.
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@ -929,7 +930,9 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
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void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
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unsigned IntCR = MakeReg(MVT::i32);
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unsigned IntCR = MakeReg(MVT::i32);
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BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
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BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
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BuildMI(BB, GPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
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bool GPOpt =
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TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor();
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BuildMI(BB, GPOpt ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
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if (Inv) {
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if (Inv) {
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unsigned Tmp1 = MakeReg(MVT::i32);
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unsigned Tmp1 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
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BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
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@ -12,7 +12,23 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "PowerPCSubtarget.h"
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#include "PowerPCSubtarget.h"
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#include "PowerPC.h"
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#include "llvm/Module.h"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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PPCTargetEnum llvm::PPCTarget = TargetDefault;
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namespace llvm {
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cl::opt<PPCTargetEnum, true>
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PPCTargetArg(cl::desc("Force generation of code for a specific PPC target:"),
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cl::values(
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clEnumValN(TargetAIX, "aix", " Enable AIX codegen"),
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clEnumValN(TargetDarwin,"darwin"," Enable Darwin codegen"),
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clEnumValEnd),
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cl::location(PPCTarget), cl::init(TargetDefault));
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cl::opt<bool> EnableGPOPT("enable-gpopt", cl::Hidden,
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cl::desc("Enable optimizations for GP cpus"));
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}
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#if defined(__APPLE__)
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#if defined(__APPLE__)
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#include <mach/mach.h>
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#include <mach/mach.h>
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@ -33,25 +49,26 @@ static boolean_t IsGP() {
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}
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}
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#endif
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#endif
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using namespace llvm;
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PPCSubtarget::PPCSubtarget(const Module &M)
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PPCSubtarget::PPCSubtarget(const Module &M)
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: TargetSubtarget(), stackAlignment(16), isGigaProcessor(false), isAIX(false),
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: StackAlignment(16), IsGigaProcessor(false), IsAIX(false), IsDarwin(false) {
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isDarwin(false) {
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// Set the boolean corresponding to the current target triple, or the default
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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// if one cannot be determined, to true.
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const std::string& TT = M.getTargetTriple();
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const std::string& TT = M.getTargetTriple();
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if (TT.length() > 5) {
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if (TT.length() > 5) {
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isDarwin = TT.find("darwin") != std::string::npos;
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IsDarwin = TT.find("darwin") != std::string::npos;
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#if defined(__APPLE__)
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#if defined(__APPLE__)
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isGigaProcessor = IsGP();
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IsGigaProcessor = IsGP();
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#endif
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#endif
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} else if (TT.empty()) {
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} else if (TT.empty()) {
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#if defined(_POWER)
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#if defined(_POWER)
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isAIX = true;
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IsAIX = true;
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#elif defined(__APPLE__)
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#elif defined(__APPLE__)
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isDarwin = true;
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IsDarwin = true;
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isGigaProcessor = IsGP();
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IsGigaProcessor = IsGP();
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#endif
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#endif
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}
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}
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// If GP opts are forced on by the commandline, do so now.
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if (EnableGPOPT) IsGigaProcessor = true;
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}
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}
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@ -23,12 +23,12 @@ class PPCSubtarget : public TargetSubtarget {
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protected:
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protected:
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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unsigned StackAlignment;
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/// Used by the ISel to turn in optimizations for POWER4-derived architectures
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/// Used by the ISel to turn in optimizations for POWER4-derived architectures
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bool isGigaProcessor;
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bool IsGigaProcessor;
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bool isAIX;
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bool IsAIX;
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bool isDarwin;
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bool IsDarwin;
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public:
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public:
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/// This constructor initializes the data members to match that
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/// This constructor initializes the data members to match that
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/// of the specified module.
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/// of the specified module.
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@ -38,10 +38,12 @@ public:
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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/// function for this subtarget.
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unsigned getStackAlignment() const { return stackAlignment; }
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unsigned getStackAlignment() const { return StackAlignment; }
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bool IsAIX() const { return isAIX; }
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bool isAIX() const { return IsAIX; }
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bool IsDarwin() const { return isDarwin; }
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bool isDarwin() const { return IsDarwin; }
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bool isGigaProcessor() const { return IsGigaProcessor; }
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};
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};
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} // End llvm namespace
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} // End llvm namespace
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@ -30,25 +30,8 @@
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#include <iostream>
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#include <iostream>
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using namespace llvm;
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using namespace llvm;
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bool llvm::GPOPT = false;
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static cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", cl::Hidden,
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PPCTargetEnum llvm::PPCTarget = TargetDefault;
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cl::desc("Enable LSR for PPC (beta)"));
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namespace llvm {
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cl::opt<PPCTargetEnum, true>
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PPCTargetArg(
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cl::desc("Force generation of code for a specific PPC target:"),
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cl::values(
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clEnumValN(TargetAIX, "aix", " Enable AIX codegen"),
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clEnumValN(TargetDarwin,"darwin"," Enable Darwin codegen"),
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clEnumValEnd),
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cl::location(PPCTarget), cl::init(TargetDefault));
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cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
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cl::desc("Enable LSR for PPC (beta)"),
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cl::Hidden);
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cl::opt<bool, true> EnableGPOPT("enable-gpopt", cl::Hidden,
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cl::location(GPOPT),
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cl::desc("Enable optimizations for GP cpus"));
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}
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namespace {
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namespace {
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const std::string PPC32ID = "PowerPC/32bit";
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const std::string PPC32ID = "PowerPC/32bit";
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@ -71,8 +54,8 @@ PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
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const PowerPCFrameInfo &TFI)
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const PowerPCFrameInfo &TFI)
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: TargetMachine(name, IL, TD), FrameInfo(TFI), Subtarget(M) {
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: TargetMachine(name, IL, TD), FrameInfo(TFI), Subtarget(M) {
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if (TargetDefault == PPCTarget) {
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if (TargetDefault == PPCTarget) {
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if (Subtarget.IsAIX()) PPCTarget = TargetAIX;
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if (Subtarget.isAIX()) PPCTarget = TargetAIX;
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if (Subtarget.IsDarwin()) PPCTarget = TargetDarwin;
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if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
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}
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}
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}
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}
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