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Target instruction selection should copy memoperands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-19 06:06:09 +00:00
parent 9248b3208a
commit 3c3195cbf1
1 changed files with 11 additions and 3 deletions
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14
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -2050,8 +2050,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other,
Ops, 5);
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl,
MVT::v2f64, MVT::Other, Ops, 5);
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
return Ret;
}
// Other cases are autogenerated.
break;
@ -2067,7 +2071,11 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
AM5Opc, Pred, PredReg, Chain };
return CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
return Ret;
}
// Other cases are autogenerated.
break;