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[mips][microMIPS] Implement movep instruction

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Differential Revision: http://reviews.llvm.org/D7465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228703 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2015-02-10 16:36:20 +00:00
parent b8ee890901
commit 3c53772000
11 changed files with 250 additions and 0 deletions
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78
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -151,6 +151,9 @@ class MipsAsmParser : public MCTargetAsmParser {
MipsAsmParser::OperandMatchResultTy
parseRegisterPair (OperandVector &Operands);
MipsAsmParser::OperandMatchResultTy
parseMovePRegPair(OperandVector &Operands);
MipsAsmParser::OperandMatchResultTy
parseRegisterList (OperandVector &Operands);
@ -683,6 +686,11 @@ public:
Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
}
void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
}
/// Render the operand to an MCInst as a GPR64
/// Asserts if the wrong number of operands are requested, or the operand
/// is not a k_RegisterIndex compatible with RegKind_GPR
@ -803,6 +811,12 @@ public:
Inst.addOperand(MCOperand::CreateReg(RegNo));
}
void addMovePRegPairOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
for (auto RegNo : getRegList())
Inst.addOperand(MCOperand::CreateReg(RegNo));
}
bool isReg() const override {
// As a special case until we sort out the definition of div/divu, pretend
// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
@ -867,6 +881,25 @@ public:
return 1 <= Val && Val <= 4;
}
bool isRegList() const { return Kind == k_RegList; }
bool isMovePRegPair() const {
if (Kind != k_RegList || RegList.List->size() != 2)
return false;
unsigned R0 = RegList.List->front();
unsigned R1 = RegList.List->back();
if ((R0 == Mips::A1 && R1 == Mips::A2) ||
(R0 == Mips::A1 && R1 == Mips::A3) ||
(R0 == Mips::A2 && R1 == Mips::A3) ||
(R0 == Mips::A0 && R1 == Mips::S5) ||
(R0 == Mips::A0 && R1 == Mips::S6) ||
(R0 == Mips::A0 && R1 == Mips::A1) ||
(R0 == Mips::A0 && R1 == Mips::A2) ||
(R0 == Mips::A0 && R1 == Mips::A3))
return true;
return false;
}
StringRef getToken() const {
assert(Kind == k_Token && "Invalid access!");
@ -1053,6 +1086,12 @@ public:
(RegIdx.Index >= 2 && RegIdx.Index <= 7) ||
RegIdx.Index == 17);
}
bool isMM16AsmRegMoveP() const {
if (!(isRegIdx() && RegIdx.Kind))
return false;
return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
(RegIdx.Index >= 16 && RegIdx.Index <= 20));
}
bool isFGRAsmReg() const {
// AFGR64 is $0-$15 but we handle this in getAFGR64()
return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
@ -3036,6 +3075,45 @@ MipsAsmParser::parseRegisterPair(OperandVector &Operands) {
return MatchOperand_Success;
}
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseMovePRegPair(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands;
SmallVector<unsigned, 10> Regs;
if (Parser.getTok().isNot(AsmToken::Dollar))
return MatchOperand_ParseFail;
SMLoc S = Parser.getTok().getLoc();
if (parseAnyRegister(TmpOperands) != MatchOperand_Success)
return MatchOperand_ParseFail;
MipsOperand *Reg = &static_cast<MipsOperand &>(*TmpOperands.back());
unsigned RegNo = isGP64bit() ? Reg->getGPR64Reg() : Reg->getGPR32Reg();
Regs.push_back(RegNo);
SMLoc E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::Comma)) {
Error(E, "',' expected");
return MatchOperand_ParseFail;
}
// Remove comma.
Parser.Lex();
if (parseAnyRegister(TmpOperands) != MatchOperand_Success)
return MatchOperand_ParseFail;
Reg = &static_cast<MipsOperand &>(*TmpOperands.back());
RegNo = isGP64bit() ? Reg->getGPR64Reg() : Reg->getGPR32Reg();
Regs.push_back(RegNo);
Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this));
return MatchOperand_Success;
}
MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
MCSymbolRefExpr::VariantKind VK =

65
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -114,6 +114,11 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@ -439,6 +444,10 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
namespace llvm {
extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
TheMips64elTarget;
@ -1005,6 +1014,17 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@ -1835,6 +1855,51 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
switch (RegPair) {
default:
return MCDisassembler::Fail;
case 0:
Inst.addOperand(MCOperand::CreateReg(Mips::A1));
Inst.addOperand(MCOperand::CreateReg(Mips::A2));
break;
case 1:
Inst.addOperand(MCOperand::CreateReg(Mips::A1));
Inst.addOperand(MCOperand::CreateReg(Mips::A3));
break;
case 2:
Inst.addOperand(MCOperand::CreateReg(Mips::A2));
Inst.addOperand(MCOperand::CreateReg(Mips::A3));
break;
case 3:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::S5));
break;
case 4:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::S6));
break;
case 5:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::A1));
break;
case 6:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::A2));
break;
case 7:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::A3));
break;
}
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));

34
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -942,6 +942,40 @@ MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
}
unsigned
MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned res = 0;
if (MI.getOperand(0).getReg() == Mips::A1 &&
MI.getOperand(1).getReg() == Mips::A2)
res = 0;
else if (MI.getOperand(0).getReg() == Mips::A1 &&
MI.getOperand(1).getReg() == Mips::A3)
res = 1;
else if (MI.getOperand(0).getReg() == Mips::A2 &&
MI.getOperand(1).getReg() == Mips::A3)
res = 2;
else if (MI.getOperand(0).getReg() == Mips::A0 &&
MI.getOperand(1).getReg() == Mips::S5)
res = 3;
else if (MI.getOperand(0).getReg() == Mips::A0 &&
MI.getOperand(1).getReg() == Mips::S6)
res = 4;
else if (MI.getOperand(0).getReg() == Mips::A0 &&
MI.getOperand(1).getReg() == Mips::A1)
res = 5;
else if (MI.getOperand(0).getReg() == Mips::A0 &&
MI.getOperand(1).getReg() == Mips::A2)
res = 6;
else if (MI.getOperand(0).getReg() == Mips::A0 &&
MI.getOperand(1).getReg() == Mips::A3)
res = 7;
return res;
}
unsigned
MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,

4
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
View File

@ -208,6 +208,10 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

14
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -258,6 +258,20 @@ class B16_FM {
let Inst{9-0} = offset;
}
class MOVEP_FM_MM16 {
bits<3> dst_regs;
bits<3> rt;
bits<3> rs;
bits<16> Inst;
let Inst{15-10} = 0x21;
let Inst{9-7} = dst_regs;
let Inst{6-4} = rt;
let Inst{3-1} = rs;
let Inst{0} = 0;
}
//===----------------------------------------------------------------------===//
// MicroMIPS 32-bit Instruction Formats
//===----------------------------------------------------------------------===//

23
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -192,6 +192,28 @@ class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
let DecoderMethod = "DecodeMemMMImm12";
}
/// A register pair used by movep instruction.
def MovePRegPairAsmOperand : AsmOperandClass {
let Name = "MovePRegPair";
let ParserMethod = "parseMovePRegPair";
let PredicateMethod = "isMovePRegPair";
}
def movep_regpair : Operand<i32> {
let EncoderMethod = "getMovePRegPairOpValue";
let ParserMatchClass = MovePRegPairAsmOperand;
let PrintMethod = "printRegisterList";
let DecoderMethod = "DecodeMovePRegPair";
let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
}
class MovePMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
NoItinerary, FrmR> {
let isReMaterializable = 1;
}
/// A register pair used by load/store pair instructions.
def RegPairAsmOperand : AsmOperandClass {
let Name = "RegPair";
@ -572,6 +594,7 @@ def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
IsAsCheapAsAMove;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;

19
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -302,6 +302,16 @@ def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
V0, V1, A0, A1, A2, A3)>;
def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
// Reserved
ZERO,
// Callee save
S1,
// Return Values and Arguments
V0, V1,
// Callee save
S0, S2, S3, S4)>;
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
// Reserved
ZERO_64, AT_64,
@ -459,6 +469,11 @@ def GPRMM16AsmOperandZero : MipsAsmRegOperand {
let PredicateMethod = "isMM16AsmRegZero";
}
def GPRMM16AsmOperandMoveP : MipsAsmRegOperand {
let Name = "GPRMM16AsmRegMoveP";
let PredicateMethod = "isMM16AsmRegMoveP";
}
def ACC64DSPAsmOperand : MipsAsmRegOperand {
let Name = "ACC64DSPAsmReg";
let PredicateMethod = "isACCAsmReg";
@ -522,6 +537,10 @@ def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
let ParserMatchClass = GPRMM16AsmOperandZero;
}
def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {
let ParserMatchClass = GPRMM16AsmOperandMoveP;
}
def GPR64Opnd : RegisterOperand<GPR64> {
let ParserMatchClass = GPR64AsmOperand;
}

3
test/MC/Disassembler/Mips/micromips.txt
View File

@ -501,3 +501,6 @@
# CHECK: sdbbp16 14
0x46 0xce
# CHECK: movep $5, $6, $2, $3
0x84 0x34

3
test/MC/Disassembler/Mips/micromips_le.txt
View File

@ -501,3 +501,6 @@
# CHECK: sdbbp16 14
0xce 0x46
# CHECK: movep $5, $6, $2, $3
0x34 0x84

3
test/MC/Mips/micromips-16-bit-instructions.s
View File

@ -43,6 +43,7 @@
# CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
# CHECK-EL: mflo $9 # encoding: [0x49,0x46]
# CHECK-EL: move $25, $1 # encoding: [0x21,0x0f]
# CHECK-EL: movep $5, $6, $2, $3 # encoding: [0x34,0x84]
# CHECK-EL: jrc $9 # encoding: [0xa9,0x45]
# CHECK-NEXT: jalr $9 # encoding: [0xc9,0x45]
# CHECK-EL: jraddiusp 20 # encoding: [0x05,0x47]
@ -97,6 +98,7 @@
# CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
# CHECK-EB: mflo $9 # encoding: [0x46,0x49]
# CHECK-EB: move $25, $1 # encoding: [0x0f,0x21]
# CHECK-EB: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
# CHECK-EB: jrc $9 # encoding: [0x45,0xa9]
# CHECK-NEXT: jalr $9 # encoding: [0x45,0xc9]
# CHECK-EB: jraddiusp 20 # encoding: [0x47,0x05]
@ -149,6 +151,7 @@
mfhi $9
mflo $9
move $25, $1
movep $5, $6, $2, $3
jrc $9
jalr $9
jraddiusp 20

4
test/MC/Mips/micromips-invalid.s
View File

@ -69,3 +69,7 @@
pref 256, 8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
beqz16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
bnez16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction