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misched: Initial code for building an MI level scheduling DAG

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-01-14 02:17:18 +00:00
parent 7ebcaf4cf9
commit 3c58ba8ea7
4 changed files with 112 additions and 20 deletions
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14
lib/CodeGen/ScheduleDAGInstrs.h
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@@ -20,6 +20,7 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallSet.h"
#include <map>
@@ -107,7 +108,8 @@ namespace llvm {
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
/// UnitLatencies flag forces single-cycle data dependencies.
/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
/// the def-side latency only.
bool UnitLatencies;
/// Defs, Uses - Remember where defs and uses of each register are as we
@@ -117,6 +119,13 @@ namespace llvm {
std::vector<std::vector<SUnit *> > Defs;
std::vector<std::vector<SUnit *> > Uses;
// Virtual register Defs and Uses.
//
// TODO: Eliminate VRegUses by creating SUnits in a prepass and looking up
// the live range's reaching def.
IndexedMap<SUnit*, VirtReg2IndexFunctor> VRegDefs;
IndexedMap<std::vector<SUnit*>, VirtReg2IndexFunctor> VRegUses;
/// PendingLoads - Remember where unknown loads are after the most recent
/// unknown store, as we iterate. As with Defs and Uses, this is here
/// to minimize construction/destruction.
@@ -211,7 +220,8 @@ namespace llvm {
protected:
void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
void addVirtRegDeps(SUnit *SU, unsigned OperIdx);
void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
};
}